b190056fa9
Add the OPP table taken from the vendor u200 and u211 DTS. The Amlogic G12A SoC seems to available in 3 types : - low-speed: up to 1,8GHz - mid-speed: up to 1,908GHz - high-speed: up to 2.1GHz And the S905X2 opp voltages are slightly higher than the S905D2 OPP voltages for the low-speed table. This adds the conservative OPP table with the S905X2 higher voltages and the maximum low-speed OPP frequency. The values were tested to be stable on an Amlogic U200 Reference Board, SeiRobotics SEI510 and X96 Max Set-Top-Boxes running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
116 lines
2.0 KiB
Plaintext
116 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
|
|
*/
|
|
|
|
#include "meson-g12-common.dtsi"
|
|
|
|
/ {
|
|
compatible = "amlogic,g12a";
|
|
|
|
cpus {
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x0>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x1>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x2>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0 0x3>;
|
|
enable-method = "psci";
|
|
next-level-cache = <&l2>;
|
|
};
|
|
|
|
l2: l2-cache0 {
|
|
compatible = "cache";
|
|
};
|
|
};
|
|
|
|
cpu_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-100000000 {
|
|
opp-hz = /bits/ 64 <100000000>;
|
|
opp-microvolt = <731000>;
|
|
};
|
|
|
|
opp-250000000 {
|
|
opp-hz = /bits/ 64 <250000000>;
|
|
opp-microvolt = <731000>;
|
|
};
|
|
|
|
opp-500000000 {
|
|
opp-hz = /bits/ 64 <500000000>;
|
|
opp-microvolt = <731000>;
|
|
};
|
|
|
|
opp-667000000 {
|
|
opp-hz = /bits/ 64 <666666666>;
|
|
opp-microvolt = <731000>;
|
|
};
|
|
|
|
opp-1000000000 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <731000>;
|
|
};
|
|
|
|
opp-1200000000 {
|
|
opp-hz = /bits/ 64 <1200000000>;
|
|
opp-microvolt = <731000>;
|
|
};
|
|
|
|
opp-1398000000 {
|
|
opp-hz = /bits/ 64 <1398000000>;
|
|
opp-microvolt = <761000>;
|
|
};
|
|
|
|
opp-1512000000 {
|
|
opp-hz = /bits/ 64 <1512000000>;
|
|
opp-microvolt = <791000>;
|
|
};
|
|
|
|
opp-1608000000 {
|
|
opp-hz = /bits/ 64 <1608000000>;
|
|
opp-microvolt = <831000>;
|
|
};
|
|
|
|
opp-1704000000 {
|
|
opp-hz = /bits/ 64 <1704000000>;
|
|
opp-microvolt = <861000>;
|
|
};
|
|
|
|
opp-1800000000 {
|
|
opp-hz = /bits/ 64 <1800000000>;
|
|
opp-microvolt = <981000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&sd_emmc_a {
|
|
amlogic,dram-access-quirk;
|
|
};
|