cea4314790
- !LLSC now only needs a single spinlock for atomics and bitops
- Some codegen changes (slight bloat) with generic bitops
1. code increase due to LD-check-atomic paradigm vs. unconditonal
atomic (but dirty'ing the cache line even if set already).
So despite increase, generic is right thing to do.
2. code decrease (but use of costlier instructions such as DIV vs.
shifts based math) due to signed arithmetic.
This needs to be revisited seperately.
arc:
static inline int test_bit(unsigned int nr, const volatile unsigned long *addr)
^^^^^^^^^^^^
generic:
static inline int test_bit(int nr, const volatile unsigned long *addr)
^^^
Link: https://lore.kernel.org/r/20180830135749.GA13005@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
[vgupta: wrote patch based on Will's poc, analysed codegen diffs]
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
129 lines
3.7 KiB
C
129 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef __ASM_ARC_SMP_H
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#define __ASM_ARC_SMP_H
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#ifdef CONFIG_SMP
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/threads.h>
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#define raw_smp_processor_id() (current_thread_info()->cpu)
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/* including cpumask.h leads to cyclic deps hence this Forward declaration */
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struct cpumask;
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/*
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* APIs provided by arch SMP code to generic code
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*/
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extern void arch_send_call_function_single_ipi(int cpu);
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extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
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/*
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* APIs provided by arch SMP code to rest of arch code
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*/
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extern void __init smp_init_cpus(void);
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extern void first_lines_of_secondary(void);
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extern const char *arc_platform_smp_cpuinfo(void);
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/*
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* API expected BY platform smp code (FROM arch smp code)
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*
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* smp_ipi_irq_setup:
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* Takes @cpu and @hwirq to which the arch-common ISR is hooked up
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*/
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extern int smp_ipi_irq_setup(int cpu, irq_hw_number_t hwirq);
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/*
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* struct plat_smp_ops - SMP callbacks provided by platform to ARC SMP
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*
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* @info: SoC SMP specific info for /proc/cpuinfo etc
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* @init_early_smp: A SMP specific h/w block can init itself
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* Could be common across platforms so not covered by
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* mach_desc->init_early()
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* @init_per_cpu: Called for each core so SMP h/w block driver can do
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* any needed setup per cpu (e.g. IPI request)
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* @cpu_kick: For Master to kickstart a cpu (optionally at a PC)
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* @ipi_send: To send IPI to a @cpu
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* @ips_clear: To clear IPI received at @irq
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*/
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struct plat_smp_ops {
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const char *info;
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void (*init_early_smp)(void);
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void (*init_per_cpu)(int cpu);
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void (*cpu_kick)(int cpu, unsigned long pc);
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void (*ipi_send)(int cpu);
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void (*ipi_clear)(int irq);
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};
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/* TBD: stop exporting it for direct population by platform */
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extern struct plat_smp_ops plat_smp_ops;
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#else /* CONFIG_SMP */
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static inline void smp_init_cpus(void) {}
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static inline const char *arc_platform_smp_cpuinfo(void)
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{
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return "";
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}
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#endif /* !CONFIG_SMP */
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/*
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* ARC700 doesn't support atomic Read-Modify-Write ops.
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* Originally Interrupts had to be disabled around code to gaurantee atomicity.
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* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
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* based on retry-if-irq-in-atomic (with hardware assist).
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* However despite these, we provide the IRQ disabling variant
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*
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* (1) These insn were introduced only in 4.10 release. So for older released
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* support needed.
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*
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* (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
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* gaurantted by the platform (not something which core handles).
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* Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
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* disabling for atomicity.
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*
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* However exported spinlock API is not usable due to cyclic hdr deps
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* (even after system.h disintegration upstream)
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* asm/bitops.h -> linux/spinlock.h -> linux/preempt.h
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* -> linux/thread_info.h -> linux/bitops.h -> asm/bitops.h
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*
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* So the workaround is to use the lowest level arch spinlock API.
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* The exported spinlock API is smart enough to be NOP for !CONFIG_SMP,
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* but same is not true for ARCH backend, hence the need for 2 variants
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*/
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#ifndef CONFIG_ARC_HAS_LLSC
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#include <linux/irqflags.h>
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#ifdef CONFIG_SMP
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#include <asm/spinlock.h>
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extern arch_spinlock_t smp_atomic_ops_lock;
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#define atomic_ops_lock(flags) do { \
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local_irq_save(flags); \
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arch_spin_lock(&smp_atomic_ops_lock); \
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} while (0)
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#define atomic_ops_unlock(flags) do { \
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arch_spin_unlock(&smp_atomic_ops_lock); \
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local_irq_restore(flags); \
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} while (0)
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#else /* !CONFIG_SMP */
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#define atomic_ops_lock(flags) local_irq_save(flags)
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#define atomic_ops_unlock(flags) local_irq_restore(flags)
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#endif /* !CONFIG_SMP */
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#endif /* !CONFIG_ARC_HAS_LLSC */
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#endif
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