Stephen Boyd
f9fca892af
Merge branches 'clk-xilinx', 'clk-kunit', 'clk-cs2000' and 'clk-renesas' into clk-next ...
- Kunit tests for clk-gate implementation
- Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
support for dynamic mode
* clk-xilinx:
clk: zynqmp: replace warn_once with pr_debug for failed clock ops
* clk-kunit:
clk: gate: Add some kunit test suites
* clk-cs2000:
clk: cs2000-cp: convert driver to regmap
clk: cs2000-cp: freeze config during register fiddling
clk: cs2000-cp: make clock skip setting configurable
clk: cs2000-cp: add support for dynamic mode
clk: cs2000-cp: Make aux output function controllable
dt-bindings: clock: cs2000-cp: document cirrus,dynamic-mode
dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flag
dt-bindings: clock: cs2000-cp: document aux-output-source
dt-bindings: clock: convert cs2000-cp bindings to yaml
* clk-renesas:
dt-bindings: clock: renesas: Make example 'clocks' parsable
clk: rs9: Add Renesas 9-series PCIe clock generator driver
clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
clk: renesas: r8a779f0: Add PFC clock
clk: renesas: r8a779f0: Add I2C clocks
clk: renesas: r8a779f0: Add WDT clock
clk: renesas: r8a779f0: Fix RSW2 clock divider
clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
dt-bindings: clock: renesas: Document RZ/V2L SoC
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
clk: renesas: r8a779a0: Add CANFD module clock
clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
clk: renesas: r8a7799[05]: Add MLP clocks
clk: renesas: r8a779f0: Add SYS-DMAC clocks
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f9fca892af
