930a8a015d
Fix "HDMA_V0_REMOTEL_STOP_INT_EN" typo error
Fixes: e74c39573d ("dmaengine: dw-edma: Add support for native HDMA")
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Link: https://lore.kernel.org/r/20240129-b4-feature_hdma_mainline-v7-3-8e8c1acb7a46@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
130 lines
2.6 KiB
C
130 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Cai Huoqing
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* Synopsys DesignWare HDMA v0 reg
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*
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* Author: Cai Huoqing <cai.huoqing@linux.dev>
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*/
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#ifndef _DW_HDMA_V0_REGS_H
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#define _DW_HDMA_V0_REGS_H
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#include <linux/dmaengine.h>
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#define HDMA_V0_MAX_NR_CH 8
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#define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6)
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#define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5)
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#define HDMA_V0_LOCAL_STOP_INT_EN BIT(4)
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#define HDMA_V0_REMOTE_STOP_INT_EN BIT(3)
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#define HDMA_V0_ABORT_INT_MASK BIT(2)
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#define HDMA_V0_STOP_INT_MASK BIT(0)
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#define HDMA_V0_LINKLIST_EN BIT(0)
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#define HDMA_V0_CONSUMER_CYCLE_STAT BIT(1)
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#define HDMA_V0_CONSUMER_CYCLE_BIT BIT(0)
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#define HDMA_V0_DOORBELL_START BIT(0)
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#define HDMA_V0_CH_STATUS_MASK GENMASK(1, 0)
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struct dw_hdma_v0_ch_regs {
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u32 ch_en; /* 0x0000 */
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u32 doorbell; /* 0x0004 */
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u32 prefetch; /* 0x0008 */
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u32 handshake; /* 0x000c */
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union {
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u64 reg; /* 0x0010..0x0014 */
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struct {
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u32 lsb; /* 0x0010 */
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u32 msb; /* 0x0014 */
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};
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} llp;
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u32 cycle_sync; /* 0x0018 */
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u32 transfer_size; /* 0x001c */
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union {
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u64 reg; /* 0x0020..0x0024 */
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struct {
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u32 lsb; /* 0x0020 */
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u32 msb; /* 0x0024 */
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};
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} sar;
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union {
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u64 reg; /* 0x0028..0x002c */
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struct {
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u32 lsb; /* 0x0028 */
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u32 msb; /* 0x002c */
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};
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} dar;
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u32 watermark_en; /* 0x0030 */
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u32 control1; /* 0x0034 */
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u32 func_num; /* 0x0038 */
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u32 qos; /* 0x003c */
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u32 padding_1[16]; /* 0x0040..0x007c */
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u32 ch_stat; /* 0x0080 */
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u32 int_stat; /* 0x0084 */
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u32 int_setup; /* 0x0088 */
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u32 int_clear; /* 0x008c */
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union {
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u64 reg; /* 0x0090..0x0094 */
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struct {
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u32 lsb; /* 0x0090 */
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u32 msb; /* 0x0094 */
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};
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} msi_stop;
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union {
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u64 reg; /* 0x0098..0x009c */
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struct {
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u32 lsb; /* 0x0098 */
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u32 msb; /* 0x009c */
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};
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} msi_watermark;
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union {
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u64 reg; /* 0x00a0..0x00a4 */
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struct {
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u32 lsb; /* 0x00a0 */
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u32 msb; /* 0x00a4 */
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};
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} msi_abort;
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u32 msi_msgdata; /* 0x00a8 */
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u32 padding_2[21]; /* 0x00ac..0x00fc */
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} __packed;
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struct dw_hdma_v0_ch {
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struct dw_hdma_v0_ch_regs wr; /* 0x0000 */
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struct dw_hdma_v0_ch_regs rd; /* 0x0100 */
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} __packed;
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struct dw_hdma_v0_regs {
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struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */
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} __packed;
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struct dw_hdma_v0_lli {
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u32 control;
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u32 transfer_size;
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union {
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u64 reg;
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struct {
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u32 lsb;
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u32 msb;
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};
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} sar;
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union {
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u64 reg;
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struct {
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u32 lsb;
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u32 msb;
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};
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} dar;
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} __packed;
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struct dw_hdma_v0_llp {
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u32 control;
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u32 reserved;
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union {
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u64 reg;
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struct {
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u32 lsb;
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u32 msb;
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};
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} llp;
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} __packed;
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#endif /* _DW_HDMA_V0_REGS_H */
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