2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
149 lines
3.7 KiB
C
149 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* include/asm-mips/vr41xx/vr41xx.h
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*
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* Include file for NEC VR4100 series.
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*
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* Copyright (C) 1999 Michael Klar
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* Copyright (C) 2001, 2002 Paul Mundt
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* Copyright (C) 2002 MontaVista Software, Inc.
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* Copyright (C) 2002 TimeSys Corp.
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* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
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*/
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#ifndef __NEC_VR41XX_H
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#define __NEC_VR41XX_H
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#include <linux/interrupt.h>
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/*
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* CPU Revision
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*/
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/* VR4122 0x00000c70-0x00000c72 */
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#define PRID_VR4122_REV1_0 0x00000c70
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#define PRID_VR4122_REV2_0 0x00000c70
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#define PRID_VR4122_REV2_1 0x00000c70
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#define PRID_VR4122_REV3_0 0x00000c71
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#define PRID_VR4122_REV3_1 0x00000c72
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/* VR4181A 0x00000c73-0x00000c7f */
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#define PRID_VR4181A_REV1_0 0x00000c73
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#define PRID_VR4181A_REV1_1 0x00000c74
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/* VR4131 0x00000c80-0x00000c83 */
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#define PRID_VR4131_REV1_2 0x00000c80
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#define PRID_VR4131_REV2_0 0x00000c81
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#define PRID_VR4131_REV2_1 0x00000c82
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#define PRID_VR4131_REV2_2 0x00000c83
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/* VR4133 0x00000c84- */
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#define PRID_VR4133 0x00000c84
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/*
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* Bus Control Uint
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*/
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extern unsigned long vr41xx_calculate_clock_frequency(void);
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extern unsigned long vr41xx_get_vtclock_frequency(void);
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extern unsigned long vr41xx_get_tclock_frequency(void);
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/*
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* Clock Mask Unit
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*/
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typedef enum {
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PIU_CLOCK,
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SIU_CLOCK,
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AIU_CLOCK,
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KIU_CLOCK,
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FIR_CLOCK,
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DSIU_CLOCK,
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CSI_CLOCK,
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PCIU_CLOCK,
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HSP_CLOCK,
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PCI_CLOCK,
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CEU_CLOCK,
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ETHER0_CLOCK,
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ETHER1_CLOCK
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} vr41xx_clock_t;
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extern void vr41xx_supply_clock(vr41xx_clock_t clock);
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extern void vr41xx_mask_clock(vr41xx_clock_t clock);
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/*
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* Interrupt Control Unit
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*/
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extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
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extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int));
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#define PIUINT_COMMAND 0x0040
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#define PIUINT_DATA 0x0020
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#define PIUINT_PAGE1 0x0010
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#define PIUINT_PAGE0 0x0008
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#define PIUINT_DATALOST 0x0004
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#define PIUINT_STATUSCHANGE 0x0001
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extern void vr41xx_enable_piuint(uint16_t mask);
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extern void vr41xx_disable_piuint(uint16_t mask);
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#define AIUINT_INPUT_DMAEND 0x0800
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#define AIUINT_INPUT_DMAHALT 0x0400
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#define AIUINT_INPUT_DATALOST 0x0200
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#define AIUINT_INPUT_DATA 0x0100
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#define AIUINT_OUTPUT_DMAEND 0x0008
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#define AIUINT_OUTPUT_DMAHALT 0x0004
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#define AIUINT_OUTPUT_NODATA 0x0002
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extern void vr41xx_enable_aiuint(uint16_t mask);
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extern void vr41xx_disable_aiuint(uint16_t mask);
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#define KIUINT_DATALOST 0x0004
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#define KIUINT_DATAREADY 0x0002
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#define KIUINT_SCAN 0x0001
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extern void vr41xx_enable_kiuint(uint16_t mask);
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extern void vr41xx_disable_kiuint(uint16_t mask);
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#define DSIUINT_CTS 0x0800
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#define DSIUINT_RXERR 0x0400
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#define DSIUINT_RX 0x0200
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#define DSIUINT_TX 0x0100
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#define DSIUINT_ALL 0x0f00
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extern void vr41xx_enable_dsiuint(uint16_t mask);
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extern void vr41xx_disable_dsiuint(uint16_t mask);
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#define FIRINT_UNIT 0x0010
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#define FIRINT_RX_DMAEND 0x0008
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#define FIRINT_RX_DMAHALT 0x0004
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#define FIRINT_TX_DMAEND 0x0002
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#define FIRINT_TX_DMAHALT 0x0001
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extern void vr41xx_enable_firint(uint16_t mask);
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extern void vr41xx_disable_firint(uint16_t mask);
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extern void vr41xx_enable_pciint(void);
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extern void vr41xx_disable_pciint(void);
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extern void vr41xx_enable_scuint(void);
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extern void vr41xx_disable_scuint(void);
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#define CSIINT_TX_DMAEND 0x0040
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#define CSIINT_TX_DMAHALT 0x0020
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#define CSIINT_TX_DATA 0x0010
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#define CSIINT_TX_FIFOEMPTY 0x0008
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#define CSIINT_RX_DMAEND 0x0004
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#define CSIINT_RX_DMAHALT 0x0002
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#define CSIINT_RX_FIFOEMPTY 0x0001
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extern void vr41xx_enable_csiint(uint16_t mask);
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extern void vr41xx_disable_csiint(uint16_t mask);
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extern void vr41xx_enable_bcuint(void);
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extern void vr41xx_disable_bcuint(void);
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#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
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extern void vr41xx_siu_setup(void);
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#else
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static inline void vr41xx_siu_setup(void) {}
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#endif
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#endif /* __NEC_VR41XX_H */
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