2373699a35
Currently TMC-ETR automatically selects the buffer mode from all available methods in the following sequentially fallback manner - also in that order. 1. FLAT mode with or without IOMMU 2. TMC-ETR-SG (scatter gather) mode when available 3. CATU mode when available But this order might not be ideal for all situations. For example if there is a CATU connected to ETR, it may be better to use TMC-ETR scatter gather method, rather than CATU. But hard coding such order changes will prevent us from testing or using a particular mode. This change provides following new sysfs tunables for the user to control TMC-ETR buffer mode explicitly, if required. This adds following new sysfs files for buffer mode selection purpose explicitly in the user space. /sys/bus/coresight/devices/tmc_etr<N>/buf_modes_available /sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred $ cat buf_modes_available auto flat tmc-sg catu ------------------> Supported TMC-ETR buffer modes $ echo catu > buf_mode_preferred -------> Explicit buffer mode request But explicit user request has to be within supported ETR buffer modes only. These sysfs interface files are exclussive to ETR, and hence these are not available for other TMC devices such as ETB or ETF etc. A new auto' mode (i.e ETR_MODE_AUTO) has been added to help fallback to the existing default behaviour, when user provided preferred buffer mode fails. ETR_MODE_FLAT and ETR_MODE_AUTO are always available as preferred modes. Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: James Clark <james.clark@arm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> [Fixup year in sysfs ABI documentation] Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20230818082112.554638-1-anshuman.khandual@arm.com
110 lines
4.5 KiB
Plaintext
110 lines
4.5 KiB
Plaintext
What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
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Date: November 2014
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KernelVersion: 3.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Disables write access to the Trace RAM by stopping the
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formatter after a defined number of words have been stored
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following the trigger event. Additional interface for this
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driver are expected to be added as it matures.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer.
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The value is read directly from HW register RSZ, 0x004.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Shows the value held by the TMC status register. The value
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is read directly from HW register STS, 0x00C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Shows the value held by the TMC RAM Read Pointer register
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that is used to read entries from the Trace RAM over the APB
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interface. The value is read directly from HW register RRP,
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0x014.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Shows the value held by the TMC RAM Write Pointer register
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that is used to sets the write pointer to write entries from
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the CoreSight bus into the Trace RAM. The value is read directly
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from HW register RWP, 0x018.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/trg
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Similar to "trigger_cntr" above except that this value is
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read directly from HW register TRG, 0x01C.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ctl
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Shows the value held by the TMC Control register. The value
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is read directly from HW register CTL, 0x020.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffsr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Shows the value held by the TMC Formatter and Flush Status
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register. The value is read directly from HW register FFSR,
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0x300.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/ffcr
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Shows the value held by the TMC Formatter and Flush Control
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register. The value is read directly from HW register FFCR,
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0x304.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/mode
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Shows the value held by the TMC Mode register, which
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indicate the mode the device has been configured to enact. The
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The value is read directly from the MODE register, 0x028.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/devid
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Date: March 2016
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KernelVersion: 4.7
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (Read) Indicates the capabilities of the Coresight TMC.
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The value is read directly from the DEVID register, 0xFC8,
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What: /sys/bus/coresight/devices/<memory_map>.tmc/buffer_size
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Date: December 2018
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KernelVersion: 4.19
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Size of the trace buffer for TMC-ETR when used in SYSFS
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mode. Writable only for TMC-ETR configurations. The value
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should be aligned to the kernel pagesize.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_modes_available
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Date: August 2023
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KernelVersion: 6.7
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Contact: Anshuman Khandual <anshuman.khandual@arm.com>
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Description: (Read) Shows all supported Coresight TMC-ETR buffer modes available
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for the users to configure explicitly. This file is avaialble only
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for TMC ETR devices.
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What: /sys/bus/coresight/devices/<memory_map>.tmc/buf_mode_preferred
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Date: August 2023
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KernelVersion: 6.7
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Contact: Anshuman Khandual <anshuman.khandual@arm.com>
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Description: (RW) Current Coresight TMC-ETR buffer mode selected. But user could
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only provide a mode which is supported for a given ETR device. This
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file is available only for TMC ETR devices.
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