fb026d3de3
This has been successfully tested on Netgear R6250 and two other development (unnamed) devices, all of them BCM4708 based. We also got a possitive feedback from R7000 (BCM4709) tester. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
112 lines
2.4 KiB
Plaintext
112 lines
2.4 KiB
Plaintext
/*
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* Broadcom BCM470X / BCM5301X ARM platform code.
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* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
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* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
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*
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* Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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chipcommonA {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x00001000>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@0300 {
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compatible = "ns16550";
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reg = <0x0300 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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uart1: serial@0400 {
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compatible = "ns16550";
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <100000000>;
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status = "disabled";
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};
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};
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mpcore {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19020000 0x00003000>;
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#address-cells = <1>;
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#size-cells = <1>;
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scu@0000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x0000 0x100>;
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};
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timer@0200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x0200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_periph>;
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};
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local-timer@0600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x0600 0x100>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_periph>;
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};
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x0100 0x100>;
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};
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L2: cache-controller@2000 {
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compatible = "arm,pl310-cache";
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reg = <0x2000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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/* As long as we do not have a real clock driver us this
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* fixed clock */
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clk_periph: periph {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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};
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};
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axi@18000000 {
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compatible = "brcm,bus-axi";
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reg = <0x18000000 0x1000>;
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ranges = <0x00000000 0x18000000 0x00100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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chipcommon: chipcommon@0 {
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reg = <0x00000000 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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