Florian Fainelli fb8a0b80c4 bus: brcmstb_gisb: Add support for breakpoint interrupts
GISB breakpoint interrupts can be raised when a breakpoint has been
enabled to match a specific master and/or GISB register address. Being
able to print a message, similar to those done during target abort or
timeout greatly helps debug systems.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2020-09-06 20:10:44 -07:00
..
2020-06-07 10:59:32 -07:00
2020-07-21 10:25:42 +02:00
2020-06-04 19:56:20 -07:00
2020-08-03 19:19:34 -07:00