8a2644d5f3
The Cypress cy15b104q and cy15v104q are 4Mbit serial SPI F-RAM devices. Add support for them to the spi-nor driver. The actual Device ID of this chip is 7f 7f 7f 7f 7f 7f c2 2c 04. That is six times the continuation code 7f followed by c2 for Ramtron. Unfortunately the chip sends the Device ID in reversed order, so the continuation code is not at the beginning, but instead at the end. Even more unfortunate is that when reading further the chip sends more 7f codes which means we are not even able to count the continuation codes. We can only hope that this reversed Device ID will never match any other devices ID. Collisions are improbable as of now, the solution from above is good enough. In case of future collisions one can introduce an INFO9 macro, with the downsize that struct flash_info would grow and we have lots of flashes. A more elegant solution would be to introduce dedicated flash ID tables for each bank in JESP106BA. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [tudor.ambarus@microchip.com: amend commit description with possible future solutions in case collisions occur.] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
130 lines
5.0 KiB
C
130 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static int
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s25fs_s_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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/*
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* The S25FS-S chip family reports 512-byte pages in BFPT but
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* in reality the write buffer still wraps at the safe default
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* of 256 bytes. Overwrite the page size advertised by BFPT
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* to get the writes working.
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*/
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params->page_size = 256;
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return 0;
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}
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static struct spi_nor_fixups s25fs_s_fixups = {
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.post_bfpt = s25fs_s_post_bfpt_fixups,
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};
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static const struct flash_info spansion_parts[] = {
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/* Spansion/Cypress -- single (large) sector size only, at least
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* for the chips listed here (without boot sectors).
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*/
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | USE_CLSR) },
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{ "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
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.fixups = &s25fs_s_fixups, },
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{ "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
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.fixups = &s25fs_s_fixups, },
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{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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USE_CLSR) },
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
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{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
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{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
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{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
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{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
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{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
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{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
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{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16,
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SECT_4K | SPI_NOR_DUAL_READ) },
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{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_4B_OPCODES) },
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{ "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1,
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SPI_NOR_NO_ERASE) },
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};
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static void spansion_post_sfdp_fixups(struct spi_nor *nor)
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{
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if (nor->params->size <= SZ_16M)
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return;
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nor->flags |= SNOR_F_4B_OPCODES;
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/* No small sector erase for 4-byte command set */
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = nor->info->sector_size;
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}
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static const struct spi_nor_fixups spansion_fixups = {
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.post_sfdp = spansion_post_sfdp_fixups,
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};
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const struct spi_nor_manufacturer spi_nor_spansion = {
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.name = "spansion",
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.parts = spansion_parts,
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.nparts = ARRAY_SIZE(spansion_parts),
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.fixups = &spansion_fixups,
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};
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