4fd9df10cb
Since commit d9820ff ("ARC: mm: switch pgtable_t back to struct page *")
a memory leakage problem occurs. Memory allocated for page table entries
not released during process termination. This issue can be reproduced by
a small program that allocates a large amount of memory. After several
runs, you'll see that the amount of free memory has reduced and will
continue to reduce after each run. All ARC CPUs are effected by this
issue. The issue was introduced since the kernel stable release v5.15-rc1.
As described in commit d9820ff after switch pgtable_t back to struct
page *, a pointer to "struct page" and appropriate functions are used to
allocate and free a memory page for PTEs, but the pmd_pgtable macro hasn't
changed and returns the direct virtual address from the PMD (PGD) entry.
Than this address used as a parameter in the __pte_free() and as a result
this function couldn't release memory page allocated for PTEs.
Fix this issue by changing the pmd_pgtable macro and returning pointer to
struct page.
Fixes: d9820ff76f95 ("ARC: mm: switch pgtable_t back to struct page *")
Cc: Mike Rapoport <rppt@kernel.org>
Cc: <stable@vger.kernel.org> # 5.15.x
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
188 lines
5.4 KiB
C
188 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 Synopsys, Inc. (www.synopsys.com)
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*/
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/*
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* Helpers for implemenintg paging levels
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*/
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#ifndef _ASM_ARC_PGTABLE_LEVELS_H
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#define _ASM_ARC_PGTABLE_LEVELS_H
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#if CONFIG_PGTABLE_LEVELS == 2
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/*
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* 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
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*
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* [31] 32 bit virtual address [0]
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* -------------------------------------------------------
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* | | <---------- PGDIR_SHIFT ----------> |
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* | | | <-- PAGE_SHIFT --> |
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* -------------------------------------------------------
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* | | |
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* | | --> off in page frame
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* | ---> index into Page Table
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* ----> index into Page Directory
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*
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* Given software walk, the vaddr split is arbitrary set to 11:8:13
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* However enabling of super page in a 2 level regime pegs PGDIR_SHIFT to
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* super page size.
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*/
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#if defined(CONFIG_ARC_HUGEPAGE_16M)
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#define PGDIR_SHIFT 24
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#elif defined(CONFIG_ARC_HUGEPAGE_2M)
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#define PGDIR_SHIFT 21
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#else
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/*
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* No Super page case
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* Default value provides 11:8:13 (8K), 10:10:12 (4K)
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* Limits imposed by pgtable_t only PAGE_SIZE long
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* (so 4K page can only have 1K entries: or 10 bits)
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*/
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#ifdef CONFIG_ARC_PAGE_SIZE_4K
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#define PGDIR_SHIFT 22
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#else
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#define PGDIR_SHIFT 21
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#endif
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#endif
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#else /* CONFIG_PGTABLE_LEVELS != 2 */
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/*
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* A default 3 level paging testing setup in software walked MMU
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* MMUv4 (8K page): <4> : <7> : <8> : <13>
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* A default 4 level paging testing setup in software walked MMU
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* MMUv4 (8K page): <4> : <3> : <4> : <8> : <13>
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*/
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#define PGDIR_SHIFT 28
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#if CONFIG_PGTABLE_LEVELS > 3
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#define PUD_SHIFT 25
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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#define PMD_SHIFT 21
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#endif
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#endif /* CONFIG_PGTABLE_LEVELS */
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#define PGDIR_SIZE BIT(PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE - 1))
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#define PTRS_PER_PGD BIT(32 - PGDIR_SHIFT)
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#if CONFIG_PGTABLE_LEVELS > 3
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#define PUD_SIZE BIT(PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE - 1))
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#define PTRS_PER_PUD BIT(PGDIR_SHIFT - PUD_SHIFT)
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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#define PMD_SIZE BIT(PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE - 1))
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#define PTRS_PER_PMD BIT(PUD_SHIFT - PMD_SHIFT)
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#endif
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#define PTRS_PER_PTE BIT(PMD_SHIFT - PAGE_SHIFT)
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#ifndef __ASSEMBLY__
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#if CONFIG_PGTABLE_LEVELS > 3
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#include <asm-generic/pgtable-nop4d.h>
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#elif CONFIG_PGTABLE_LEVELS > 2
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#include <asm-generic/pgtable-nopud.h>
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#else
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#include <asm-generic/pgtable-nopmd.h>
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#endif
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/*
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* 1st level paging: pgd
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*/
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#define pgd_ERROR(e) \
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pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
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#if CONFIG_PGTABLE_LEVELS > 3
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/* In 4 level paging, p4d_* macros work on pgd */
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#define p4d_none(x) (!p4d_val(x))
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#define p4d_bad(x) ((p4d_val(x) & ~PAGE_MASK))
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#define p4d_present(x) (p4d_val(x))
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#define p4d_clear(xp) do { p4d_val(*(xp)) = 0; } while (0)
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#define p4d_pgtable(p4d) ((pud_t *)(p4d_val(p4d) & PAGE_MASK))
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#define p4d_page(p4d) virt_to_page(p4d_pgtable(p4d))
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#define set_p4d(p4dp, p4d) (*(p4dp) = p4d)
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/*
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* 2nd level paging: pud
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*/
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#define pud_ERROR(e) \
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pr_crit("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
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#endif
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#if CONFIG_PGTABLE_LEVELS > 2
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/*
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* In 3 level paging, pud_* macros work on pgd
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* In 4 level paging, pud_* macros work on pud
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*/
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#define pud_none(x) (!pud_val(x))
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#define pud_bad(x) ((pud_val(x) & ~PAGE_MASK))
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#define pud_present(x) (pud_val(x))
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#define pud_clear(xp) do { pud_val(*(xp)) = 0; } while (0)
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#define pud_pgtable(pud) ((pmd_t *)(pud_val(pud) & PAGE_MASK))
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#define pud_page(pud) virt_to_page(pud_pgtable(pud))
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#define set_pud(pudp, pud) (*(pudp) = pud)
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/*
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* 3rd level paging: pmd
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*/
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#define pmd_ERROR(e) \
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pr_crit("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
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#define pmd_pfn(pmd) ((pmd_val(pmd) & PMD_MASK) >> PAGE_SHIFT)
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#define pfn_pmd(pfn,prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
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#endif
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/*
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* Due to the strange way generic pgtable level folding works, the pmd_* macros
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* - are valid even for 2 levels (which supposedly only has pgd - pte)
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* - behave differently for 2 vs. 3
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* In 2 level paging (pgd -> pte), pmd_* macros work on pgd
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* In 3+ level paging (pgd -> pmd -> pte), pmd_* macros work on pmd
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*/
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK))
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#define pmd_present(x) (pmd_val(x))
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#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
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#define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK)
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#define pmd_pfn(pmd) ((pmd_val(pmd) & PAGE_MASK) >> PAGE_SHIFT)
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#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
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#define set_pmd(pmdp, pmd) (*(pmdp) = pmd)
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#define pmd_pgtable(pmd) ((pgtable_t) pmd_page(pmd))
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/*
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* 4th level paging: pte
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*/
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#define pte_ERROR(e) \
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pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
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#define pte_clear(mm,addr,ptep) set_pte_at(mm, addr, ptep, __pte(0))
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#define pte_page(pte) pfn_to_page(pte_pfn(pte))
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#define set_pte(ptep, pte) ((*(ptep)) = (pte))
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#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
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#define pfn_pte(pfn, prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
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#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
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#ifdef CONFIG_ISA_ARCV2
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#define pmd_leaf(x) (pmd_val(x) & _PAGE_HW_SZ)
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif
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