fd915c67cd
SYS1CLK_1US represents the required number of system 1-clock cycles for one microsecond. UFS Host Controller V4.0 and above mandates to write SYS1CLK_1US_REG register and also these timer configuration needs to be called from clk scaling pre ops as per HPG. Refactor ufs_qcom_cfg_timers and add the below code support to align with HPG. a)Configure SYS1CLK_1US_REG for UFS V4 and above. b)Introduce a new argument is_pre_scale_up for ufs_qcom_cfg_timers to configure SYS1CLK_1US for max freq during prescale and link startup condition. c)Move ufs_qcom_cfg_timers from clk scaling post change ops to clk scaling pre change ops. Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20230905052400.13935-6-quic_nitirawa@quicinc.com Reviewed-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>