linux/arch/riscv
Christoph Hellwig fe9b842f72
riscv: disable SUM in the exception handler
The SUM bit is enabled at the beginning of the copy_{to,from}_user and
{get,put}_user routines, and cleared before they return.  But these user
copy helper can be interrupted by exceptions, in which case the SUM bit
will remain set, which leads to elevated privileges for the code running
in exception context, as that can now access userspace address space
unconditionally.  This frequently happens when the user copy routines
access freshly allocated user memory that hasn't been faulted in, and a
pagefault needs to be taken before the user copy routines can continue.

Fix this by unconditionally clearing SUM when the exception handler is
called - the restore code will automatically restore it based on the
saved value.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:12:38 -08:00
..
configs RISC-V: Add a basic defconfig 2018-01-07 15:14:36 -08:00
include riscv: remove unused __ARCH_HAVE_MMU define 2018-01-30 19:11:43 -08:00
kernel riscv: disable SUM in the exception handler 2018-01-30 19:12:38 -08:00
lib RISC-V: Export some expected symbols for modules 2017-11-30 10:01:10 -08:00
mm riscv: rename SR_* constants to match the spec 2018-01-07 15:14:39 -08:00
Kconfig riscv/ftrace: Add basic support 2018-01-30 19:10:54 -08:00
Makefile