Biju Das feab6a13ae arm64: dts: renesas: rz-smarc: Use versa3 clk for audio mclk
Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz).
Replace this fixed clk with the programmable versa3 clk that can provide
the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and
48kHz (with a clock of 12.2880MHz), based on audio sampling rate for
playback and record.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230825090518.87394-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05 14:25:00 +02:00
..
2023-09-05 11:01:47 -07:00
2023-09-04 15:38:24 -07:00
2023-09-01 08:02:45 -07:00
2023-08-31 12:20:12 -07:00
2023-09-05 11:01:47 -07:00
2023-09-08 12:16:52 -07:00
2023-09-05 12:37:28 -07:00
2023-09-05 10:15:22 -07:00
2023-09-07 13:52:20 -07:00
2023-08-31 12:20:12 -07:00
2023-09-05 10:09:31 -07:00
2023-09-05 12:37:28 -07:00
2023-09-05 12:37:28 -07:00
2023-09-09 14:46:57 -07:00
2023-09-05 12:37:28 -07:00
2023-09-07 10:30:17 -07:00
2023-08-31 12:20:12 -07:00