Stephen Boyd
ff060019f4
Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next ...
- Support for STM32F769
- Rework AT91 sckc DT bindings
- Fix slow RC oscillator issue on sama5d3
- AT91 sam9x60 PMC support
- SiFive FU540 PRCI and PLL support
* clk-stm32f4:
clk: stm32mp1: Add ddrperfm clock
clk: stm32: Introduce clocks of STM32F769 board
* clk-tegra:
clk: tegra: divider: Mark Memory Controller clock as read-only
clk: tegra: emc: Replace BUG() with WARN_ONCE()
clk: tegra: emc: Fix EMC max-rate clamping
clk: tegra: emc: Support multiple RAM codes
clk: tegra: emc: Don't enable EMC clock manually
clk: tegra124: Remove lock-enable bit from PLLM
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
clk: tegra: Don't enable already enabled PLLs
* clk-at91:
clk: at91: Mark struct clk_range as const
clk: at91: add sam9x60 pmc driver
dt-bindings: clk: at91: add bindings for SAM9X60 pmc
clk: at91: add sam9x60 PLL driver
clk: at91: master: Add sam9x60 support
clk: at91: usb: Add sam9x60 support
clk: at91: allow configuring generated PCR layout
clk: at91: allow configuring peripheral PCR layout
clk: at91: sckc: handle different RC startup time
clk: at91: modernize sckc binding
dt-bindings: clock: at91: new sckc bindings
* clk-sifive-fu540:
clk: sifive: add a driver for the SiFive FU540 PRCI IP block
clk: analogbits: add Wide-Range PLL library
dt-bindings: clk: add documentation for the SiFive PRCI driver
* clk-spdx:
clk: sunxi-ng: Use the correct style for SPDX License Identifier
clk: sprd: Use the correct style for SPDX License Identifier
clk: renesas: Use the correct style for SPDX License Identifier
clk: qcom: Use the correct style for SPDX License Identifier
clk: davinci: Use the correct style for SPDX License Identifier
clk: actions: Use the correct style for SPDX License Identifier
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ff060019f4