Gerhard Engleder ff46c610ab dt-bindings: net: tsnep: Allow dma-coherent ...

Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.

Add "dma-coherent" property to allow the configuration of cache coherent
DMA.

Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

2022-09-30 11:31:34 +01:00

..

bindings

dt-bindings: net: tsnep: Allow dma-coherent

2022-09-30 11:31:34 +01:00

changesets.rst

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dynamic-resolution-notes.rst

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index.rst

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kernel-api.rst

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of_unittest.rst

of: unittest: add program to process EXPECT messages

2022-02-28 15:20:32 -06:00

overlay-notes.rst

of: overlay: rework overlay apply and remove kfree()s

2022-04-25 10:56:11 -05:00

usage-model.rst

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