84e85359f4
The Devicetree bindings document does not have to say in the title that
it is a "binding", but instead just describe the hardware.
Drop trailing "bindings" in various forms (also with trailing full
stop):
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [bB]indings\?\.\?$/title: \1/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com> # ROHM
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # cpufreq
Link: https://lore.kernel.org/r/20221216163815.522628-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
102 lines
2.4 KiB
YAML
102 lines
2.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys Designware Mobile Storage Host Controller
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maintainers:
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- Ulf Hansson <ulf.hansson@linaro.org>
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# Everything else is described in the common file
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properties:
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compatible:
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enum:
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- altr,socfpga-dw-mshc
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- img,pistachio-dw-mshc
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- snps,dw-mshc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 2
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description:
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Handle to "biu" and "ciu" clocks for the
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bus interface unit clock and the card interface unit clock.
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clock-names:
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items:
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- const: biu
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- const: ciu
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altr,sysmgr-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to the sysmgr node
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- description: register offset that controls the SDMMC clock phase
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- description: register shift for the smplsel(drive in) setting
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description:
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This property is optional. Contains the phandle to System Manager block
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that contains the SDMMC clock-phase control register. The first value is
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the pointer to the sysmgr, the 2nd value is the register offset for the
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SDMMC clock phase register, and the 3rd value is the bit shift for the
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smplsel(drive in) setting.
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allOf:
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- $ref: synopsys-dw-mshc-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: altr,socfpga-dw-mshc
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then:
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properties:
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altr,sysmgr-syscon: true
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else:
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properties:
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altr,sysmgr-syscon: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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mmc@12200000 {
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compatible = "snps,dw-mshc";
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reg = <0x12200000 0x1000>;
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interrupts = <0 75 0>;
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clocks = <&clock 351>, <&clock 132>;
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clock-names = "biu", "ciu";
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dmas = <&pdma 12>;
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dma-names = "rx-tx";
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resets = <&rst 20>;
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reset-names = "reset";
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vmmc-supply = <&buck8>;
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#address-cells = <1>;
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#size-cells = <0>;
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broken-cd;
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bus-width = <8>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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max-frequency = <200000000>;
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clock-frequency = <400000000>;
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data-addr = <0x200>;
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fifo-depth = <0x80>;
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fifo-watermark-aligned;
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};
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