Claudiu Beznea 8e897cb674 ARM: dts: at91: sam9x60: fix the ddr clock for sam9x60
[ Upstream commit 9bfa2544dbd1133f0b0af4e967de3bb9c1e3a497 ]

The 2nd DDR clock for sam9x60 DDR controller is peripheral clock with
id 49.

Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221208115241.36312-1-claudiu.beznea@microchip.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
2023-02-01 08:27:07 +01:00
..
2022-11-03 23:59:15 +09:00
2022-12-02 17:41:08 +01:00