Jerome Brunet cbd69e7ae1 clk: meson: axg: spread spectrum is on mpll2
[ Upstream commit dc4e62d373f881cbf51513296a6db7806516a01a ]

After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.

Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-01-27 14:50:49 +01:00
..
2018-07-09 13:49:31 +02:00
2018-07-09 13:49:31 +02:00