Dinh Nguyen 336d708688 clk: socfpga: use clk_hw_register for a5/c5 ...

[ Upstream commit 2c2b9c6067170de2a63e7e3d9f5bb205b870de7c ]

As recommended by Stephen Boyd, convert the cyclone5/arria5 clock driver
to use the clk_hw registration method.

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210302214151.1333447-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2023-01-18 11:30:18 +01:00

..

clk-gate-a10.c

clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return

2021-05-22 10:59:17 +02:00

clk-gate-s10.c

…

clk-gate.c

clk: socfpga: use clk_hw_register for a5/c5

2023-01-18 11:30:18 +01:00

clk-periph-a10.c

…

clk-periph-s10.c

clk: socfpga: stratix10: fix rate caclulationg for cnt_clks

2019-08-29 08:28:49 +02:00

clk-periph.c

clk: socfpga: use clk_hw_register for a5/c5

2023-01-18 11:30:18 +01:00

clk-pll-a10.c

clk: socfpga: fix refcount leak

2020-01-27 14:50:08 +01:00

clk-pll-s10.c

clk: stratix10: use do_div() for 64-bit calculation

2020-10-01 13:14:33 +02:00

clk-pll.c

clk: socfpga: use clk_hw_register for a5/c5

2023-01-18 11:30:18 +01:00

clk-s10.c

clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clk

2020-10-07 08:00:05 +02:00

clk.c

…

clk.h

…

Makefile

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stratix10-clk.h

…