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linux/arch/arm/mach-tegra
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Dmitry Osipenko 7dda6ebb5b ARM: tegra: Correct PL310 Auxiliary Control Register initialization 
commit 35509737c8f958944e059d501255a0bf18361ba0 upstream.

The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.

This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:

	L2C-310: enabling full line of zeros but not enabled in Cortex-A9

Cc: <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-06-20 10:24:21 +02:00
..
board-paz00.c
device property: don't bother the drivers with struct property_set
2016-04-09 03:10:50 +02:00
board.h
ARM: tegra: Convert PMC to a driver
2014-07-17 14:58:43 +02:00
common.h
ARM: tegra: hotplug: Include missing common.h
2016-06-10 16:17:58 +02:00
cpuidle-tegra20.c
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
cpuidle-tegra30.c
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
cpuidle-tegra114.c
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
cpuidle.c
ARM: tegra: Use a function to get the chip ID
2014-07-17 13:36:41 +02:00
cpuidle.h
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
flowctrl.c
ARM: tegra: Initialize flow controller from DT
2014-08-26 11:43:55 -06:00
flowctrl.h
ARM: tegra: Initialize flow controller from DT
2014-08-26 11:43:55 -06:00
hotplug.c
ARM: tegra: hotplug: Include missing common.h
2016-06-10 16:17:58 +02:00
io.c
ARM: tegra: Sort includes alphabetically
2014-07-17 13:29:57 +02:00
iomap.h
soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers
2015-07-16 10:38:28 +02:00
irammap.h
ARM: tegra: move resume vector define to irammap.h
2013-09-17 13:44:22 -06:00
irq.c
ARM: tegra: irq: Add missing irq.h include
2016-06-10 16:18:00 +02:00
irq.h
ARM: tegra: remove old LIC support
2015-03-15 00:40:52 +00:00
Kconfig
ARM: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB
2016-06-03 12:18:13 -07:00
Makefile
ARM: v7 setup function should invalidate L1 cache
2015-06-01 11:30:26 +01:00
platsmp.c
soc/tegra: pmc: Wait for powergate state to change
2016-04-05 15:22:53 +02:00
pm-tegra20.c
ARM: tegra: Sort includes alphabetically
2014-07-17 13:29:57 +02:00
pm-tegra30.c
ARM: tegra: Sort includes alphabetically
2014-07-17 13:29:57 +02:00
pm.c
ARM: tegra: Convert PMC to a driver
2014-07-17 14:58:43 +02:00
pm.h
ARM: tegra: pm: Add tegra_cpu_do_idle() prototype
2016-06-10 16:18:01 +02:00
reset-handler.S
ARM: tegra: Fix FLOW_CTLR_HALT register clobbering by tegra_resume()
2019-12-21 10:42:31 +01:00
reset.c
ARM: v7 setup function should invalidate L1 cache
2015-06-01 11:30:26 +01:00
reset.h
ARM: SoC: platform support for v4.2
2015-06-26 11:34:35 -07:00
sleep-tegra20.S
ARM: tegra: Ensure entire dcache is flushed on entering LP0/1
2015-11-24 16:47:26 +01:00
sleep-tegra30.S
ARM: tegra: Enable PLLP bypass during Tegra124 LP1
2020-02-14 16:31:02 -05:00
sleep.h
ARM: tegra20: Store CPU "resettable" status in IRAM
2015-05-04 12:58:19 +02:00
sleep.S
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
2014-07-18 12:29:04 +01:00
tegra.c
ARM: tegra: Correct PL310 Auxiliary Control Register initialization
2020-06-20 10:24:21 +02:00