Xiu Jianfeng 3e8fd1d0fa clk: socfpga: Fix memory leak in socfpga_gate_init() ...

[ Upstream commit 0b8ba891ad4d1ef6bfa4c72efc83f9f9f855f68b ]

Free @socfpga_clk and @ops on the error path to avoid memory leak issue.

Fixes: a30a67be7b6e ("clk: socfpga: Don't have get_parent for single parent ops")
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Link: https://lore.kernel.org/r/20221123031622.63171-1-xiujianfeng@huawei.com
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2023-01-14 10:15:42 +01:00

..

clk-agilex.c

clk: socfpga: agilex: fix duplicate s2f_user0_clk

2021-10-20 11:44:58 +02:00

clk-gate-a10.c

clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return

2021-05-11 14:47:28 +02:00

clk-gate-s10.c

…

clk-gate.c

clk: socfpga: Fix memory leak in socfpga_gate_init()

2023-01-14 10:15:42 +01:00

clk-periph-a10.c

…

clk-periph-s10.c

clk: agilex/stratix10/n5x: fix how the bypass_reg is handled

2021-07-14 16:55:43 +02:00

clk-periph.c

clk: socfpga: use clk_hw_register for a5/c5

2023-01-14 10:15:41 +01:00

clk-pll-a10.c

…

clk-pll-s10.c

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00

clk-pll.c

clk: socfpga: use clk_hw_register for a5/c5

2023-01-14 10:15:41 +01:00

clk-s10.c

clk: agilex/stratix10: fix bypass representation

2021-07-14 16:55:44 +02:00

clk.c

…

clk.h

…

Makefile

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00

stratix10-clk.h

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00