Dinh Nguyen 7524fcd09c clk: socfpga: agilex: add the bypass register for s2f_usr0 clock ...

commit d17929eb1066d1c1653aae9bb4396a9f1d6602ac upstream.

Add the bypass register for the s2f_user0_clk.

Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-3-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2021-09-18 13:40:07 +02:00

..

clk-agilex.c

clk: socfpga: agilex: add the bypass register for s2f_usr0 clock

2021-09-18 13:40:07 +02:00

clk-gate-a10.c

clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return

2021-05-11 14:47:28 +02:00

clk-gate-s10.c

clk: socfpga: stratix10: use new parent data scheme

2020-05-26 19:13:05 -07:00

clk-gate.c

clk: socfpga: fix iomem pointer cast on 64-bit

2021-04-14 08:42:12 +02:00

clk-periph-a10.c

clk: socfpga: Don't reference clk_init_data after registration

2019-08-16 10:20:07 -07:00

clk-periph-s10.c

clk: agilex/stratix10/n5x: fix how the bypass_reg is handled

2021-07-14 16:55:43 +02:00

clk-periph.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-pll-a10.c

clk: socfpga: add const to _ops data structures

2020-05-26 19:13:05 -07:00

clk-pll-s10.c

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00

clk-pll.c

clk: socfpga: add const to _ops data structures

2020-05-26 19:13:05 -07:00

clk-s10.c

clk: agilex/stratix10: fix bypass representation

2021-07-14 16:55:44 +02:00

clk.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13

2019-05-21 11:28:45 +02:00

clk.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05 17:36:37 +02:00

Makefile

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00

stratix10-clk.h

clk: socfpga: agilex: add clock driver for the Agilex platform

2020-05-26 19:13:05 -07:00