Jisheng Zhang 07c1c8e320 riscv: mm: fix wrong phys_ram_base value for RV64 ...

commit b0fd4b1bf995172b9efcee23600d4f69571c321c upstream.

Currently, if 64BIT and !XIP_KERNEL, the phys_ram_base is always 0,
no matter the real start of dram reported by memblock is.

Fixes: 6d7f91d914bc ("riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion")
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Alexandre Ghiti <alex@ghiti.fr>
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2022-01-27 11:02:50 +01:00

..

cacheflush.c

riscv: Flush current cpu icache before other cpus

2021-10-04 18:24:15 -07:00

context.c

riscv: add ASID-based tlbflushing methods

2021-06-30 20:55:39 -07:00

extable.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

fault.c

riscv: Enable KFENCE for riscv64

2021-06-30 20:55:41 -07:00

hugetlbpage.c

hugetlbfs: remove hugetlb_add_hstate() warning for existing hstate

2020-06-03 20:09:46 -07:00

init.c

riscv: mm: fix wrong phys_ram_base value for RV64

2022-01-27 11:02:50 +01:00

kasan_init.c

riscv: Fix asan-stack clang build

2021-10-29 08:54:50 -07:00

Makefile

riscv: Fixup patch_text panic in ftrace

2021-01-14 15:09:04 -08:00

pageattr.c

RISC-V Patches for the 5.11 Merge Window, Part 1

2020-12-18 10:43:07 -08:00

physaddr.c

riscv: Introduce structure that group all variables regarding kernel mapping

2021-07-05 18:04:00 -07:00

ptdump.c

riscv: Fix PTDUMP output now BPF region moved back to module region

2021-07-06 15:21:27 -07:00

tlbflush.c

riscv: add ASID-based tlbflushing methods

2021-06-30 20:55:39 -07:00