linux

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Andi Kleen ec903b6daa x86/perf: Avoid warning for Arch LBR without XSAVE

[ Upstream commit 8c16dc047b5dd8f7b3bf4584fa75733ea0dde7dc ]

Some hypervisors support Arch LBR, but without the LBR XSAVE support.
The current Arch LBR init code prints a warning when the xsave size (0) is
unexpected. Avoid printing the warning for the "no LBR XSAVE" case.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20211215204029.150686-1-ak@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

2022-02-16 12:56:11 +01:00

amd

perf/x86/amd/ibs: Add bitfield definitions in new <asm/amd-ibs.h> header

2021-08-26 09:14:36 +02:00

intel

x86/perf: Avoid warning for Arch LBR without XSAVE

2022-02-16 12:56:11 +01:00

zhaoxin

x86: Fix various typos in comments

2021-03-18 15:31:53 +01:00

core.c

perf: Protect perf_guest_cbs with RCU