Swapnil Jakhade 8b5d69613b phy: cadence: Sierra: Fix to get correct parent for mux clocks ...

[ Upstream commit da08aab940092a050a4fb2857ed9479d2b0e03c4 ]

Fix get_parent() callback to return the correct index of the parent for
PLL_CMNLC1 clock. Add a separate table of register values corresponding
to the parent index for PLL_CMNLC1. Update set_parent() callback
accordingly.

Fixes: 28081b72859f ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)")
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2022-01-27 11:04:16 +01:00

..

cdns-dphy.c

phy: cadence: convert to devm_platform_ioremap_resource

2020-11-16 12:47:46 +05:30

Kconfig

phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)

2021-03-31 16:43:21 +05:30

Makefile

phy: cadence: salvo: add salvo phy driver

2020-05-07 09:46:36 +05:30

phy-cadence-salvo.c

phy: cadence: convert to devm_platform_ioremap_resource

2020-11-16 12:47:46 +05:30

phy-cadence-sierra.c

phy: cadence: Sierra: Fix to get correct parent for mux clocks

2022-01-27 11:04:16 +01:00

phy-cadence-torrent.c

phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation

2021-08-17 15:42:44 +05:30