Guo Ren 1509e93916 riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte ...

commit 950b879b7f0251317d26bae0687e72592d607532 upstream.

In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
in __sync_icache_dcache()"), we found RISC-V has the same issue as the
previous arm64. The previous implementation didn't guarantee the correct
sequence of operations, which means flush_icache_all() hasn't been
called when the PG_dcache_clean was set. That would cause a risk of page
synchronization.

Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230127035306.1819561-1-guoren@kernel.org
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2023-02-22 12:50:33 +01:00

..

cacheflush.c

riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte

2023-02-22 12:50:33 +01:00

context.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

extable.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120

2019-05-24 17:39:02 +02:00

fault.c

exit: Add and use make_task_dead.

2023-02-06 07:52:49 +01:00

hugetlbpage.c

riscv: Introduce huge page support for 32/64bit kernel

2019-07-03 15:23:38 -07:00

init.c

riscv: Add sfence.vma after early page table changes

2020-09-23 12:40:43 +02:00

ioremap.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

Makefile

riscv: move the TLB flush logic out of line

2019-09-05 01:54:51 -07:00

sifive_l2_cache.c

riscv: mark some code and data as file-static

2019-10-28 00:46:01 -07:00

tlbflush.c

riscv: move the TLB flush logic out of line

2019-09-05 01:54:51 -07:00