Frederik Haxel 9b2f64ba99 riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro ...

[ Upstream commit 5daa3726410288075ba73c336bb2e80d6b06aa4d ]

During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.

Fixes: bee7fbc38579 ("RISC-V CPU Idle Support")
Fixes: e7681beba992 ("RISC-V: Split out the XIP fixups into their own file")

Signed-off-by: Frederik Haxel <haxel@fzi.de>
Link: https://lore.kernel.org/r/20231212130116.848530-3-haxel@fzi.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2024-01-25 15:35:50 -08:00

..

asm

riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro

2024-01-25 15:35:50 -08:00

uapi/asm

RISC-V Patches for the 6.6 Merge Window, Part 2 (try 2)

2023-09-09 14:25:11 -07:00