Jesse Taube abb84c4620 RISC-V: fix vector insn load/store width mask ...

[ Upstream commit 04a2aef59cfe192aa99020601d922359978cc72a ]

RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
Replace GENMASK(3, 0) with GENMASK(2, 0).

Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240606182800.415831-1-jesse@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2024-07-05 09:33:53 +02:00

..

asm

RISC-V: fix vector insn load/store width mask

2024-07-05 09:33:53 +02:00

uapi/asm

RISC-V: Update AT_VECTOR_SIZE_ARCH for new AT_MINSIGSTKSZ

2024-04-10 16:35:58 +02:00