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Signed-off-by: Ján Tomko <jtomko@redhat.com>
Reviewed-by: Erik Skultety <eskultet@redhat.com>
Reviewed-by: Neal Gompa <ngompa13@gmail.com>
This commit is contained in:
Ján Tomko 2020-08-26 00:46:53 +02:00
parent 4216192929
commit 4e7a27b610
7 changed files with 42 additions and 42 deletions
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2
docs/formatdomain.rst
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@ -1036,7 +1036,7 @@ Memory Tuning
QEMU and KVM are strongly advised not to set this limit as domain may get
killed by the kernel if the guess is too low, and determining the memory
needed for a process to run is an `undecidable
problem <http://en.wikipedia.org/wiki/Undecidable_problem>`__; that said, if
problem <https://en.wikipedia.org/wiki/Undecidable_problem>`__; that said, if
you already set ``locked`` in `memory backing <#elementsMemoryBacking>`__
because your workload demands it, you'll have to take into account the
specifics of your deployment and figure out a value for ``hard_limit`` that

2
docs/internals/rpc.html.in
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@ -22,7 +22,7 @@
<p>
libvirt uses a simple, variable length, packet based RPC protocol.
All structured data within packets is encoded using the
<a href="http://en.wikipedia.org/wiki/External_Data_Representation">XDR standard</a>
<a href="https://en.wikipedia.org/wiki/External_Data_Representation">XDR standard</a>
as currently defined by <a href="https://tools.ietf.org/html/rfc4506">RFC 4506</a>.
On any connection running the RPC protocol, there can be multiple
programs active, each supporting one or more versions. A program

2
docs/remote.html.in
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@ -58,7 +58,7 @@ Remote libvirt supports a range of transports:
</p>
<dl>
<dt><code>tls</code></dt>
<dd><a href="http://en.wikipedia.org/wiki/Transport_Layer_Security" title="Transport Layer Security">TLS</a>
<dd><a href="https://en.wikipedia.org/wiki/Transport_Layer_Security" title="Transport Layer Security">TLS</a>
1.0 (SSL 3.1) authenticated and encrypted TCP/IP socket, usually
listening on a public port number. To use this you will need to
<a href="tlscerts.html" title="Generating TLS certificates">generate client and

2
docs/securityprocess.html.in
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@ -78,7 +78,7 @@
<p>
The libvirt security team operates a policy of
<a href="http://en.wikipedia.org/wiki/Responsible_disclosure">responsible disclosure</a>.
<a href="https://en.wikipedia.org/wiki/Responsible_disclosure">responsible disclosure</a>.
As such any security issue reported, that is not already publicly disclosed
elsewhere, will have an embargo date assigned. Members of the security team agree
not to publicly disclose any details of the security issue until the embargo

2
docs/tlscerts.html.in
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@ -135,7 +135,7 @@ server. May be enabled and disabled in the <a href="#Remote_libvirtd_configurat
</ul>
<p>
For full certificate checking you will need to have certificates
issued by a recognised <a href="http://en.wikipedia.org/wiki/Certificate_authority">Certificate
issued by a recognised <a href="https://en.wikipedia.org/wiki/Certificate_authority">Certificate
Authority (CA)</a> for your server(s) and all clients. To avoid the
expense of getting certificates from a commercial CA, you can set up
your own CA and tell your server(s) and clients to trust certificates

2
src/rpc/virnetclient.c
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@ -1838,7 +1838,7 @@ static void virNetClientIOUpdateCallback(virNetClientPtr client,
*
* We call this dance 'passing the buck'
*
* http://en.wikipedia.org/wiki/Passing_the_buck
* https://en.wikipedia.org/wiki/Passing_the_buck
*
* "Buck passing or passing the buck is the action of transferring
* responsibility or blame unto another person. It is also used as

72
src/util/virarch.h
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@ -25,49 +25,49 @@
typedef enum {
VIR_ARCH_NONE,
VIR_ARCH_ALPHA, /* Alpha 64 BE http://en.wikipedia.org/wiki/DEC_Alpha */
VIR_ARCH_ARMV6L, /* ARMv6 32 LE http://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_ARMV7L, /* ARMv7 32 LE http://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_ARMV7B, /* ARMv7 32 BE http://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_ALPHA, /* Alpha 64 BE https://en.wikipedia.org/wiki/DEC_Alpha */
VIR_ARCH_ARMV6L, /* ARMv6 32 LE https://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_ARMV7L, /* ARMv7 32 LE https://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_ARMV7B, /* ARMv7 32 BE https://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_AARCH64, /* ARMv8 64 LE http://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_CRIS, /* ETRAX 32 LE http://en.wikipedia.org/wiki/ETRAX_CRIS */
VIR_ARCH_I686, /* x86 32 LE http://en.wikipedia.org/wiki/X86 */
VIR_ARCH_ITANIUM, /* Itanium 64 LE http://en.wikipedia.org/wiki/Itanium */
VIR_ARCH_LM32, /* MilkyMist 32 BE http://en.wikipedia.org/wiki/Milkymist */
VIR_ARCH_AARCH64, /* ARMv8 64 LE https://en.wikipedia.org/wiki/ARM_architecture */
VIR_ARCH_CRIS, /* ETRAX 32 LE https://en.wikipedia.org/wiki/ETRAX_CRIS */
VIR_ARCH_I686, /* x86 32 LE https://en.wikipedia.org/wiki/X86 */
VIR_ARCH_ITANIUM, /* Itanium 64 LE https://en.wikipedia.org/wiki/Itanium */
VIR_ARCH_LM32, /* MilkyMist 32 BE https://en.wikipedia.org/wiki/Milkymist */
VIR_ARCH_M68K, /* m68k 32 BE http://en.wikipedia.org/wiki/Motorola_68000_family */
VIR_ARCH_MICROBLAZE, /* Microblaze 32 BE http://en.wikipedia.org/wiki/MicroBlaze */
VIR_ARCH_MICROBLAZEEL, /* Microblaze 32 LE http://en.wikipedia.org/wiki/MicroBlaze */
VIR_ARCH_MIPS, /* MIPS 32 BE http://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_MIPSEL, /* MIPS 32 LE http://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_M68K, /* m68k 32 BE https://en.wikipedia.org/wiki/Motorola_68000_family */
VIR_ARCH_MICROBLAZE, /* Microblaze 32 BE https://en.wikipedia.org/wiki/MicroBlaze */
VIR_ARCH_MICROBLAZEEL, /* Microblaze 32 LE https://en.wikipedia.org/wiki/MicroBlaze */
VIR_ARCH_MIPS, /* MIPS 32 BE https://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_MIPSEL, /* MIPS 32 LE https://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_MIPS64, /* MIPS 64 BE http://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_MIPS64EL, /* MIPS 64 LE http://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_OR32, /* OpenRisc 32 BE http://en.wikipedia.org/wiki/OpenRISC#QEMU_support */
VIR_ARCH_PARISC, /* PA-Risc 32 BE http://en.wikipedia.org/wiki/PA-RISC */
VIR_ARCH_PARISC64, /* PA-Risc 64 BE http://en.wikipedia.org/wiki/PA-RISC */
VIR_ARCH_MIPS64, /* MIPS 64 BE https://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_MIPS64EL, /* MIPS 64 LE https://en.wikipedia.org/wiki/MIPS_architecture */
VIR_ARCH_OR32, /* OpenRisc 32 BE https://en.wikipedia.org/wiki/OpenRISC#QEMU_support */
VIR_ARCH_PARISC, /* PA-Risc 32 BE https://en.wikipedia.org/wiki/PA-RISC */
VIR_ARCH_PARISC64, /* PA-Risc 64 BE https://en.wikipedia.org/wiki/PA-RISC */
VIR_ARCH_PPC, /* PowerPC 32 BE http://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPCLE, /* PowerPC 32 LE http://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPC64, /* PowerPC 64 BE http://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPC64LE, /* PowerPC 64 LE http://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPCEMB, /* PowerPC 32 BE http://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPC, /* PowerPC 32 BE https://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPCLE, /* PowerPC 32 LE https://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPC64, /* PowerPC 64 BE https://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPC64LE, /* PowerPC 64 LE https://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_PPCEMB, /* PowerPC 32 BE https://en.wikipedia.org/wiki/PowerPC */
VIR_ARCH_RISCV32, /* RISC-V 32 LE http://en.wikipedia.org/wiki/RISC-V */
VIR_ARCH_RISCV64, /* RISC-V 64 LE http://en.wikipedia.org/wiki/RISC-V */
VIR_ARCH_S390, /* S390 32 BE http://en.wikipedia.org/wiki/S390 */
VIR_ARCH_S390X, /* S390 64 BE http://en.wikipedia.org/wiki/S390x */
VIR_ARCH_SH4, /* SuperH4 32 LE http://en.wikipedia.org/wiki/SuperH */
VIR_ARCH_RISCV32, /* RISC-V 32 LE https://en.wikipedia.org/wiki/RISC-V */
VIR_ARCH_RISCV64, /* RISC-V 64 LE https://en.wikipedia.org/wiki/RISC-V */
VIR_ARCH_S390, /* S390 32 BE https://en.wikipedia.org/wiki/S390 */
VIR_ARCH_S390X, /* S390 64 BE https://en.wikipedia.org/wiki/S390x */
VIR_ARCH_SH4, /* SuperH4 32 LE https://en.wikipedia.org/wiki/SuperH */
VIR_ARCH_SH4EB, /* SuperH4 32 BE http://en.wikipedia.org/wiki/SuperH */
VIR_ARCH_SPARC, /* Sparc 32 BE http://en.wikipedia.org/wiki/Sparc */
VIR_ARCH_SPARC64, /* Sparc 64 BE http://en.wikipedia.org/wiki/Sparc */
VIR_ARCH_UNICORE32, /* UniCore 32 LE http://en.wikipedia.org/wiki/Unicore */
VIR_ARCH_X86_64, /* x86 64 LE http://en.wikipedia.org/wiki/X86 */
VIR_ARCH_SH4EB, /* SuperH4 32 BE https://en.wikipedia.org/wiki/SuperH */
VIR_ARCH_SPARC, /* Sparc 32 BE https://en.wikipedia.org/wiki/Sparc */
VIR_ARCH_SPARC64, /* Sparc 64 BE https://en.wikipedia.org/wiki/Sparc */
VIR_ARCH_UNICORE32, /* UniCore 32 LE https://en.wikipedia.org/wiki/Unicore */
VIR_ARCH_X86_64, /* x86 64 LE https://en.wikipedia.org/wiki/X86 */
VIR_ARCH_XTENSA, /* XTensa 32 LE http://en.wikipedia.org/wiki/Xtensa#Processor_Cores */
VIR_ARCH_XTENSAEB, /* XTensa 32 BE http://en.wikipedia.org/wiki/Xtensa#Processor_Cores */
VIR_ARCH_XTENSA, /* XTensa 32 LE https://en.wikipedia.org/wiki/Xtensa#Processor_Cores */
VIR_ARCH_XTENSAEB, /* XTensa 32 BE https://en.wikipedia.org/wiki/Xtensa#Processor_Cores */
VIR_ARCH_LAST,
} virArch;