From cad8054ece285d1712880cd108e8a39f833f7e88 Mon Sep 17 00:00:00 2001
From: Peter Krempa <pkrempa@redhat.com>
Date: Wed, 8 Feb 2012 12:43:07 +0100
Subject: [PATCH] cpu: Add cpu definition for Intel Sandy Bridge cpu type

This patch adds support for the new tsc-deadline feature flag
and a new model to the supported model list describing the
Intel Sandy Bridge platform.
---
 src/cpu/cpu_map.xml | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/src/cpu/cpu_map.xml b/src/cpu/cpu_map.xml
index 8f80dd99dc..6af9c40900 100644
--- a/src/cpu/cpu_map.xml
+++ b/src/cpu/cpu_map.xml
@@ -160,6 +160,9 @@
     <feature name='popcnt'> <!-- CPUID_EXT_POPCNT -->
       <cpuid function='0x00000001' ecx='0x00800000'/>
     </feature>
+    <feature name='tsc-deadline'>
+      <cpuid function='0x00000001' ecx='0x01000000'/>
+    </feature>
     <feature name='aes'>
       <cpuid function='0x00000001' ecx='0x02000000'/>
     </feature>
@@ -593,6 +596,48 @@
       <feature name='aes'/>
     </model>
 
+    <model name='SandyBridge'>
+      <vendor name='Intel'/>
+      <feature name='aes'/>
+      <feature name='apic'/>
+      <feature name='avx'/>
+      <feature name='clflush'/>
+      <feature name='cmov'/>
+      <feature name='cx16'/>
+      <feature name='cx8'/>
+      <feature name='de'/>
+      <feature name='fpu'/>
+      <feature name='fxsr'/>
+      <feature name='lahf_lm'/>
+      <feature name='lm'/>
+      <feature name='mca'/>
+      <feature name='mce'/>
+      <feature name='mmx'/>
+      <feature name='msr'/>
+      <feature name='mtrr'/>
+      <feature name='nx'/>
+      <feature name='pae'/>
+      <feature name='pat'/>
+      <feature name='pclmuldq'/>
+      <feature name='pge'/>
+      <feature name='pni'/>
+      <feature name='popcnt'/>
+      <feature name='pse'/>
+      <feature name='pse36'/>
+      <feature name='rdtscp'/>
+      <feature name='sep'/>
+      <feature name='sse'/>
+      <feature name='sse2'/>
+      <feature name='sse4.1'/>
+      <feature name='sse4.2'/>
+      <feature name='ssse3'/>
+      <feature name='syscall'/>
+      <feature name='tsc'/>
+      <feature name='tsc-deadline'/>
+      <feature name='x2apic'/>
+      <feature name='xsave'/>
+    </model>
+
     <model name='Opteron_G1'>
       <vendor name='AMD'/>
       <feature name='sse2'/>