2 Commits

Author	SHA1	Message	Date
Jiri Denemark	7bb4ce9761	cpu: Add Broadwell-IBRS CPU model ... This is a variant of Broadwell with indirect branch prediction protection. The only difference between Broadwell and Broadwell-IBRS is the added "spec-ctrl" feature. The Broadwell-IBRS model in QEMU is a bit different since Broadwell got several additional features since we added it in cpu_map.xml: abm, arat, f16c, rdrand, vme, xsaveopt Adding them only to the -IBRS variant would confuse our CPU detection code. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com>	2018-01-17 17:07:04 +01:00
Jiri Denemark	69e4eb047f	cputest: Add data for Intel(R) Xeon(R) CPU E5-2623 v4 ... The CPU contains the updated microcode for CVE-2017-5715. The *-guest.xml and *-json.xml CPU definitions use Skylake-Client CPU model rather than Broadwell. This is similar to Xeon-E5-2650-v4 and it is caused by our CPU model selection code when no model matches the CPU signature (family + model). We'd need to maintain a complete list of CPU signatures for our CPU models to fix this. Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com>	2018-01-17 17:07:02 +01:00