5 Commits

Author	SHA1	Message	Date
Jiri Denemark	96a39aad70	cpu_map: Add missing AMD SVM features ... Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>	2020-06-19 21:59:31 +02:00
Jiri Denemark	892b7c70f6	cpu_map: Add missing x86 features in 0x80000008 CPUID leaf ... Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>	2020-06-19 21:59:31 +02:00
Ani Sinha	1d17f881a2	cpu: add CLZERO CPUID support for AMD platforms ... Qemu commit e900135dcfb67 ("i386: Add CPUID bit for CLZERO and XSAVEERPTR") adds support for CLZERO CPUID bit. This commit extends support for this CPUID bit into libvirt. Signed-off-by: Ani Sinha <ani.sinha@nutanix.com> Message-Id: <1575371352-99055-1-git-send-email-ani.sinha@nutanix.com> Reviewed-by: Jiri Denemark <jdenemar@redhat.com>	2019-12-16 13:04:14 +01:00
Brijesh Singh	a0b628432a	cpu: Add new EPYC CPU model ... Add a new CPU model called 'EPYC' to model processors from AMD EPYC family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx). The following features bits have been added/removed compare to Opteron_G5 Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw, fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha xsaveopt, xsavec, xgetbv1, arat Removed: xop, fma4, tbm The patch is depend on EPYC CPU model supported introduced in qemu [1] [1] https://patchwork.kernel.org/patch/9902205/ Cc: Tom Lendacky <Thomas.Lendacky@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com>	2017-09-07 13:53:32 +02:00
Jiri Denemark	5c83b3603c	tests: Add CPUID data for AMD EPYC 7601 32-Core Processor ... Signed-off-by: Jiri Denemark <jdenemar@redhat.com> Reviewed-by: Pavel Hrdina <phrdina@redhat.com>	2017-09-07 13:53:32 +02:00