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d60012b4e7
All Intel Haswell processors (except Xeon E7 v3 with stepping >= 4) have TSX disabled by microcode update. As not all CPUs are guaranteed to be patched with microcode updates we need to explicitly disable TSX on affected CPUs to avoid its accidental usage. https://bugzilla.redhat.com/show_bug.cgi?id=1406791 Signed-off-by: Jiri Denemark <jdenemar@redhat.com>
30 lines
699 B
XML
30 lines
699 B
XML
<cpu>
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<arch>x86_64</arch>
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<model>Haswell-noTSX</model>
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<vendor>Intel</vendor>
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<feature name='vme'/>
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<feature name='ds'/>
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<feature name='acpi'/>
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<feature name='ss'/>
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<feature name='ht'/>
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<feature name='tm'/>
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<feature name='pbe'/>
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<feature name='dtes64'/>
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<feature name='monitor'/>
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<feature name='ds_cpl'/>
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<feature name='vmx'/>
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<feature name='smx'/>
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<feature name='est'/>
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<feature name='tm2'/>
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<feature name='xtpr'/>
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<feature name='pdcm'/>
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<feature name='osxsave'/>
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<feature name='f16c'/>
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<feature name='rdrand'/>
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<feature name='arat'/>
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<feature name='tsc_adjust'/>
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<feature name='pdpe1gb'/>
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<feature name='abm'/>
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<feature name='invtsc'/>
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</cpu>
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