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import gdb-19990422 snapshot

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This commit is contained in:
Stan Shebs 1999-04-26 18:30:24 +00:00
parent 9f89d263d1
commit 581bf2caf1
120 changed files with 7592 additions and 6732 deletions
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21
readline/ChangeLog
View File

@ -1,3 +1,24 @@
1999-04-22 Jason Molenda (jsm@bugshack.cygnus.com)
* Makefile.in (install): Make comment about this change more explicit.
1999-04-22 Jason Molenda (jsm@bugshack.cygnus.com)
* Makefile.in (install): Don't install the final libreadline.a
or .h files.
Tue Mar 23 10:56:08 1999 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
Patches from Robert Hoehne <robert.hoehne@gmx.net>:
* display.c: Change some terminal calls to work on DJGPP.
* terminal.c: Likewise.
* Makefile.in: Remove . from the VPATH directive.
Tue Mar 9 14:58:13 1999 Geoffrey Noer <noer@cygnus.com>
* support/config.sub: Recognize cygwin*, not just cygwin32.
Tue Feb 9 10:38:57 1999 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
* configure.in: Do not use the ./support directory.

20
sim/ChangeLog
View File

@ -1,24 +1,18 @@
1999-04-08 Nick Clifton <nickc@cygnus.com>
* configure.in: Add support for MCore target.
* configure: Regenerate.
1999-03-14 Stan Shebs <shebs@andros.cygnus.com>
* Makefile.in (FLAGS_TO_PASS, TARGET_FLAGS_TO_PASS): Remove
RUNTEST instead of commenting out, fixes portability problem.
1999-02-10 Doug Evans <devans@casey.cygnus.com>
* configure.in (sparc*): Configure sparc subdir if --with-cgen or
--with-cgen-sim.
* configure: Rebuild.
1999-02-08 Nick Clifton <nickc@cygnus.com>
* configure.in: Add support for StrongARM target.
* configure: Regenerate.
1999-02-02 Doug Evans <devans@casey.cygnus.com>
* configure.in (sparc*): Configure sparc subdir if --with-cgen.
* configure: Rebuild.
1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com)
* configure.in: Require autoconf 2.12.1 or higher.
@ -40,8 +34,8 @@ Fri Sep 25 10:12:19 1998 Christopher Faylor <cgf@cygnus.com>
Thu May 28 14:59:46 1998 Jillian Ye <jillian@cygnus.com>
* Makefile.in: Take RUNTEST out of FLAG_TO_PASS
so that make check can be invoked recursively.
* Makefile.in: Take RUNTEST out of FLAGS_TO_PASS so that make
check can be invoked recursively.
Wed Apr 29 12:38:53 1998 Mark Alexander <marka@cygnus.com>

22
sim/arm/ChangeLog
View File

@ -1,3 +1,25 @@
1999-04-06 Keith Seitz <keiths@cygnus.com>
* wrapper.c (stop_simulator): New global.
(sim_stop): Set sim state to STOP and set
stop_simulator.
(sim_resume): Reset stop_simulator.
(sim_stop_reason): If stop_simulator is set, tell gdb
that the we took SIGINT.
* armemu.c (ARMul_Emulate26): Don't loop forever. Stop if
stop_simulator is set.
1999-04-02 Keith Seitz <keiths@cygnus.com>
* armemu.c (ARMul_Emulate26): If NEED_UI_LOOP_HOOK, call ui_loop_hook
whenever the counter expires.
* Makefile.in (SIM_EXTRA_CFLAGS): Include define NEED_UI_LOOP_HOOK.
1999-03-24 Nick Clifton <nickc@cygnus.com>
* armemu.c (ARMul_Emulate26): Handle new breakpoint value.
* thumbemu.c (ARMul_ThumbDecode): Handle new breakpoint value.
Mon Sep 14 09:00:05 1998 Nick Clifton <nickc@cygnus.com>
* wrapper.c (sim_open): Set endianness according to BFD or command

2
sim/arm/Makefile.in
View File

@ -18,7 +18,7 @@
## COMMON_PRE_CONFIG_FRAG
SIM_EXTRA_CFLAGS = -DMODET
SIM_EXTRA_CFLAGS = -DMODET -DNEED_UI_LOOP_HOOK
SIM_OBJS = armcopro.o armemu26.o armemu32.o arminit.o armos.o armsupp.o \
armvirt.o bag.o thumbemu.o wrapper.o sim-load.o

42
sim/arm/armemu.c
View File

@ -18,6 +18,7 @@
#include "armdefs.h"
#include "armemu.h"
#include "armos.h"
static ARMword GetDPRegRHS(ARMul_State *state, ARMword instr) ;
static ARMword GetDPSRegRHS(ARMul_State *state, ARMword instr) ;
@ -43,6 +44,19 @@ static unsigned MultiplyAdd64(ARMul_State *state, ARMword instr,int signextend,i
#define LDEFAULT (0) /* default : do nothing */
#define LSCC (1) /* set condition codes on result */
#ifdef NEED_UI_LOOP_HOOK
/* How often to run the ui_loop update, when in use */
#define UI_LOOP_POLL_INTERVAL 0x32000
/* Counter for the ui_loop_hook update */
static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
/* Actual hook to call to run through gdb's gui event loop */
extern int (*ui_loop_hook) (int);
#endif /* NEED_UI_LOOP_HOOK */
extern int stop_simulator;
/***************************************************************************\
* short-hand macros for LDR/STR *
\***************************************************************************/
@ -2166,10 +2180,20 @@ mainswitch:
break ;
case 0x7f : /* Load Byte, WriteBack, Pre Inc, Reg */
if (BIT(4)) {
ARMul_UndefInstr(state,instr) ;
break ;
}
if (BIT(4))
{
/* Check for the special breakpoint opcode.
This value should correspond to the value defined
as ARM_BE_BREAKPOINT in gdb/arm-tdep.c. */
if (BITS (0,19) == 0xfdefe)
{
if (! ARMul_OSHandleSWI (state, SWI_Breakpoint))
ARMul_Abort (state, ARMul_SWIV);
}
else
ARMul_UndefInstr(state,instr) ;
break ;
}
UNDEF_LSRBaseEQOffWb ;
UNDEF_LSRBaseEQDestWb ;
UNDEF_LSRPCBaseWb ;
@ -2549,11 +2573,19 @@ mainswitch:
donext:
#endif
#ifdef NEED_UI_LOOP_HOOK
if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
{
ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
ui_loop_hook (0);
}
#endif /* NEED_UI_LOOP_HOOK */
if (state->Emulate == ONCE)
state->Emulate = STOP;
else if (state->Emulate != RUN)
break;
} while (1) ; /* do loop */
} while (!stop_simulator) ; /* do loop */
state->decoded = decoded ;
state->loaded = loaded ;

4
sim/arm/thumbemu.c
View File

@ -29,6 +29,7 @@ existing ARM simulator. */
#include "armdefs.h"
#include "armemu.h"
#include "armos.h"
/* Decode a 16bit Thumb instruction. The instruction is in the low
16-bits of the tinstr field, with the following Thumb instruction
@ -356,6 +357,9 @@ ARMul_ThumbDecode (state,pc,tinstr,ainstr)
/* Breakpoint must be handled specially. */
if ((tinstr & 0x00FF) == 0x18)
*ainstr |= ((tinstr & 0x00FF) << 16);
/* New breakpoint value. See gdb/arm-tdep.c */
else if ((tinstr & 0x00FF) == 0xFE)
* ainstr |= SWI_Breakpoint;
else
*ainstr |= (tinstr & 0x00FF);
}

14
sim/arm/wrapper.c
View File

@ -50,6 +50,8 @@ static int verbosity;
/* Non-zero to set big endian mode. */
static int big_endian;
int stop_simulator;
static void
init ()
{
@ -154,7 +156,9 @@ int
sim_stop (sd)
SIM_DESC sd;
{
return 0;
state->Emulate = STOP;
stop_simulator = 1;
return 1;
}
void
@ -163,6 +167,7 @@ sim_resume (sd, step, siggnal)
int step, siggnal;
{
state->EndCondition = 0;
stop_simulator = 0;
if (step)
{
@ -435,7 +440,12 @@ sim_stop_reason (sd, reason, sigrc)
enum sim_stop *reason;
int *sigrc;
{
if (state->EndCondition == 0)
if (stop_simulator)
{
*reason = sim_stopped;
*sigrc = SIGINT;
}
else if (state->EndCondition == 0)
{
*reason = sim_exited;
*sigrc = state->Reg[0] & 255;

53
sim/common/ChangeLog
View File

@ -1,3 +1,56 @@
Fri Apr 16 16:43:22 1999 Doug Evans <devans@charmed.cygnus.com>
* sim-core.c (device_error,device_io_read_buffer,
device_io_write_buffer): Delete decls.
* sim-core.h: Put them here.
* sim-core.c (sim_core_read_buffer): Pass sd to device_io_read_buffer.
(sim_core_write_buffer): Pass sd to device_io_write_buffer.
* sim-n-core.h (sim_core_read_aligned_N): Ditto.
(sim_core_write_aligned_N): Ditto.
1999-04-14 Stephane Carrez <stcarrez@worldnet.fr>
* sim-memopt.c (sim_memory_uninstall): Don't look into
free()d memory.
1999-04-14 Doug Evans <devans@casey.cygnus.com>
* cgen-utils.scm (virtual_insn_entries): Update attribute definition.
1999-04-13 Doug Evans <devans@casey.cygnus.com>
* sim-core.c (sim_core_read_buffer): Handle NULL cpu when WITH_DEVICES.
(sim_core_write_buffer): Ditto.
1999-04-02 Keith Seitz <keiths@cygnus.com>
* sim-io.c (sim_io_poll_quit): Only call the poll_quit callback
after the interval counter has expired.
(POLL_QUIT_INTERVAL): Define. Used to tweak the frequency of
poll_quit callbacks. May be overridden by Makefile.
(poll_quit_counter): New global.
* sim-events.c: Remove all mentions of ui_loop_hook. The
host callback "poll_quit" will serve the purpose.
* run.c: Add definition of ui_loop_hook when NEED_UI_LOOP_HOOK
is defined.
* nrun.c: Remove declaration of ui_loop_hook.
Wed Mar 31 18:55:41 1999 Doug Evans <devans@canuck.cygnus.com>
* cgen-run.c (sim_resume): Don't tell main loop to run "forever"
if being used by gdb.
1999-03-22 Doug Evans <devans@casey.cygnus.com>
* cgen-types.h (XF,TF): Tweak.
* cgen-ops.h: Redo inline support. Delete DI_FN_SUPPORT,
in cgen-types.h.
(SUBWORD*,JOIN*): Define.
* cgen-trace.c (sim_cgen_disassemble_insn): Update, base_insn_bitsize
moved into cpu descriptor.
* sim-model.h (MACH): New member `num'.
1999-02-09 Doug Evans <devans@casey.cygnus.com>
* Make-common.in (CGEN_READ_SCM): Renamed from CGEN_MAIN_SCM.

148
sim/common/cgen-ops.h
View File

@ -1,5 +1,5 @@
/* Semantics ops support for CGEN-based simulators.
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This file is part of the GNU Simulators.
@ -23,6 +23,13 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#ifndef CGEN_SEM_OPS_H
#define CGEN_SEM_OPS_H
#if defined (__GNUC__) && ! defined (SEMOPS_DEFINE_INLINE)
#define SEMOPS_DEFINE_INLINE
#define SEMOPS_INLINE extern inline
#else
#define SEMOPS_INLINE
#endif
/* Semantic operations.
At one point this file was machine generated. Maybe it will be again. */
@ -357,6 +364,7 @@ extern DI EXTSIDI PARAMS ((SI));
#else
#define EXTSIDI(x) ((DI) (SI) (x))
#endif
#if defined (SF_FN_SUPPORT) || defined (DF_FN_SUPPORT)
extern DF EXTSFDF PARAMS ((SF));
#else
@ -387,6 +395,7 @@ extern TF EXTXFTF PARAMS ((XF));
#else
#define EXTXFTF(x) ((TF) (XF) (x))
#endif
#define ZEXTBIQI(x) ((QI) (BI) (x))
#define ZEXTBIHI(x) ((HI) (BI) (x))
#define ZEXTBISI(x) ((SI) (BI) (x))
@ -413,6 +422,7 @@ extern DI ZEXTSIDI PARAMS ((SI));
#else
#define ZEXTSIDI(x) ((DI) (USI) (x))
#endif
#define TRUNCQIBI(x) ((BI) (QI) (x))
#define TRUNCHIBI(x) ((BI) (HI) (x))
#define TRUNCHIQI(x) ((QI) (HI) (x))
@ -439,6 +449,7 @@ extern SI TRUNCDISI PARAMS ((DI));
#else
#define TRUNCDISI(x) ((SI) (DI) (x))
#endif
#if defined (DF_FN_SUPPORT) || defined (SF_FN_SUPPORT)
extern SF TRUNCDFSF PARAMS ((DF));
#else
@ -469,6 +480,7 @@ extern XF TRUNCTFXF PARAMS ((TF));
#else
#define TRUNCTFXF(x) ((XF) (TF) (x))
#endif
#if defined (SF_FN_SUPPORT)
extern SF FLOATQISF PARAMS ((QI));
#else
@ -549,6 +561,7 @@ extern TF FLOATDITF PARAMS ((DI));
#else
#define FLOATDITF(x) ((TF) (DI) (x))
#endif
#if defined (SF_FN_SUPPORT)
extern SF UFLOATQISF PARAMS ((QI));
#else
@ -629,6 +642,7 @@ extern TF UFLOATDITF PARAMS ((DI));
#else
#define UFLOATDITF(x) ((TF) (UDI) (x))
#endif
#if defined (SF_FN_SUPPORT)
extern BI FIXSFBI PARAMS ((SF));
#else
@ -729,6 +743,7 @@ extern DI FIXTFDI PARAMS ((TF));
#else
#define FIXTFDI(x) ((DI) (TF) (x))
#endif
#if defined (SF_FN_SUPPORT)
extern QI UFIXSFQI PARAMS ((SF));
#else
@ -810,15 +825,118 @@ extern DI UFIXTFDI PARAMS ((TF));
#define UFIXTFDI(x) ((UDI) (TF) (x))
#endif
/* Semantic support utilities. */
#ifdef __GNUC__
/* Composing/decomposing the various types. */
#ifdef SEMOPS_DEFINE_INLINE
#define SEMOPS_INLINE
SEMOPS_INLINE SF
SUBWORDSISF (SIM_CPU *cpu, SI in)
{
union { SI in; SF out; } x;
x.in = in;
return x.out;
}
SEMOPS_INLINE SI
SUBWORDSFSI (SIM_CPU *cpu, SF in)
{
union { SF in; SI out; } x;
x.in = in;
return x.out;
}
SEMOPS_INLINE SI
SUBWORDDISI (SIM_CPU *cpu, DI in, int word)
{
/* ??? endianness issues undecided */
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
{
if (word == 0)
return (UDI) in >> 32;
else
return in;
}
else
{
if (word == 1)
return (UDI) in >> 32;
else
return in;
}
}
SEMOPS_INLINE SI
SUBWORDDFSI (SIM_CPU *cpu, DF in, int word)
{
/* ??? endianness issues undecided */
union { DF in; SI out[2]; } x;
x.in = in;
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
return x.out[word];
else
return x.out[!word];
}
SEMOPS_INLINE SI
SUBWORDTFSI (SIM_CPU *cpu, TF in, int word)
{
/* ??? endianness issues undecided */
union { TF in; SI out[4]; } x;
x.in = in;
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
return x.out[word];
else
return x.out[word ^ 3];
}
SEMOPS_INLINE DI
JOINSIDI (SIM_CPU *cpu, SI x0, SI x1)
{
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
return MAKEDI (x0, x1);
else
return MAKEDI (x1, x0);
}
SEMOPS_INLINE DF
JOINSIDF (SIM_CPU *cpu, SI x0, SI x1)
{
union { SI in[2]; DF out; } x;
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
x.in[0] = x0, x.in[1] = x1;
else
x.in[1] = x0, x.in[0] = x1;
return x.out;
}
SEMOPS_INLINE TF
JOINSITF (SIM_CPU *cpu, SI x0, SI x1, SI x2, SI x3)
{
union { SI in[4]; TF out; } x;
if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
x.in[0] = x0, x.in[1] = x1, x.in[2] = x2, x.in[3] = x3;
else
x.in[3] = x0, x.in[2] = x1, x.in[1] = x2, x.in[0] = x3;
return x.out;
}
#else
#define SEMOPS_INLINE extern inline
#endif
SF SUBWORDSISF (SIM_CPU *, SI);
SI SUBWORDSFSI (SIM_CPU *, SF);
SI SUBWORDDISI (SIM_CPU *, DI, int);
SI SUBWORDDFSI (SIM_CPU *, DF, int);
SI SUBWORDTFSI (SIM_CPU *, TF, int);
DI JOINSIDI (SIM_CPU *, SI, SI);
DF JOINSIDF (SIM_CPU *, SI, SI);
TF JOINSITF (SIM_CPU *, SI, SI, SI, SI);
#endif /* SUBWORD,JOIN */
/* Semantic support utilities. */
#ifdef SEMOPS_DEFINE_INLINE
SEMOPS_INLINE SI
ADDCSI (SI a, SI b, BI c)
@ -877,21 +995,5 @@ UBI SUBCFSI (SI, SI, BI);
UBI SUBOFSI (SI, SI, BI);
#endif
/* DI mode support if "long long" doesn't exist.
At one point CGEN supported K&R C compilers, and ANSI C compilers without
"long long". One can argue the various merits of keeping this in or
throwing it out. I went to the trouble of adding it so for the time being
I'm leaving it in. */
#ifdef DI_FN_SUPPORT
DI make_struct_di (SI, SI);
/* FIXME: needed? */
DI CONVHIDI (HI);
DI CONVSIDI (SI);
SI CONVDISI (DI);
#endif /* DI_FN_SUPPORT */
#endif /* CGEN_SEM_OPS_H */

8
sim/common/cgen-run.c
View File

@ -93,9 +93,13 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
way to identify this case. */
int max_insns = (step
? 1
: (nr_cpus == 1 /*&& wip:no-events*/)
: (nr_cpus == 1
/*&& wip:no-events*/
/* Don't do this if running under gdb, need to
poll ui for events. */
&& STATE_OPEN_KIND (sd) == SIM_OPEN_STANDALONE)
? 0
: 4); /*FIXME: magic number*/
: 8); /*FIXME: magic number*/
int fast_p = STATE_RUN_FAST_P (sd);
sim_events_preprocess (sd, last_cpu_nr >= nr_cpus, next_cpu_nr >= nr_cpus);

8
sim/common/cgen-trace.c
View File

@ -380,12 +380,12 @@ sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
insn_length);
switch (min (CGEN_BASE_INSN_SIZE, insn_length))
switch (min (cd->base_insn_bitsize, insn_bit_length))
{
case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
case 1 : insn_value = insn_buf.bytes[0]; break;
case 2 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
case 4 : insn_value = T2H_4 (insn_buf.words[0]); break;
case 8 : insn_value = insn_buf.bytes[0]; break;
case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
default: abort ();
}

8
sim/common/cgen-types.h
View File

@ -100,10 +100,10 @@ extern DI make_struct_di (SI, SI);
/* FIXME: Need to provide libraries if these aren't appropriate for target,
or user's needs. */
typedef float SF;
typedef double DF;
typedef double XF; /* FIXME: configure, provide library */
typedef double TF; /* FIXME: configure, provide library */
typedef float SF; /* FIXME: struct */
typedef double DF; /* FIXME: struct */
typedef struct { SI parts[3]; } XF; /* FIXME: configure, provide library */
typedef struct { SI parts[4]; } TF; /* FIXME: configure, provide library */
/* These are used to record extracted raw data from an instruction, among other
things. It must be a host data type, and not a target one. */

18
sim/common/cgen-utils.c
View File

@ -59,28 +59,22 @@ const char *mode_names[] = {
static const CGEN_IBASE virtual_insn_entries[] =
{
{
VIRTUAL_INSN_X_INVALID, "--invalid--", NULL, 0,
{ CGEN_INSN_NBOOL_ATTRS, V, { 0 } }
VIRTUAL_INSN_X_INVALID, "--invalid--", NULL, 0, { V, { 0 } }
},
{
VIRTUAL_INSN_X_BEFORE, "--before--", NULL, 0,
{ CGEN_INSN_NBOOL_ATTRS, V, { 0 } }
VIRTUAL_INSN_X_BEFORE, "--before--", NULL, 0, { V, { 0 } }
},
{
VIRTUAL_INSN_X_AFTER, "--after--", NULL, 0,
{ CGEN_INSN_NBOOL_ATTRS, V, { 0 } }
VIRTUAL_INSN_X_AFTER, "--after--", NULL, 0, { V, { 0 } }
},
{
VIRTUAL_INSN_X_BEGIN, "--begin--", NULL, 0,
{ CGEN_INSN_NBOOL_ATTRS, V, { 0 } }
VIRTUAL_INSN_X_BEGIN, "--begin--", NULL, 0, { V, { 0 } }
},
{
VIRTUAL_INSN_X_CHAIN, "--chain--", NULL, 0,
{ CGEN_INSN_NBOOL_ATTRS, V, { 0 } }
VIRTUAL_INSN_X_CHAIN, "--chain--", NULL, 0, { V, { 0 } }
},
{
VIRTUAL_INSN_X_CTI_CHAIN, "--cti-chain--", NULL, 0,
{ CGEN_INSN_NBOOL_ATTRS, V, { 0 } }
VIRTUAL_INSN_X_CTI_CHAIN, "--cti-chain--", NULL, 0, { V, { 0 } }
}
};

6
sim/common/nrun.c
View File

@ -206,9 +206,3 @@ usage ()
fprintf (stderr, "Run `%s --help' for full list of options.\n", myname);
exit (1);
}
#ifdef __CYGWIN32__
/* no-op GUI update hook for standalone sim */
void (*ui_loop_hook) PARAMS ((int)) = NULL;
#endif

6
sim/common/run.c
View File

@ -56,12 +56,16 @@ extern host_callback default_callback;
static char *myname;
/* NOTE: sim_size() and sim_trace() are going away */
extern int sim_trace PARAMS ((SIM_DESC sd));
extern int getopt ();
#ifdef NEED_UI_LOOP_HOOK
/* Gdb foolery. This is only needed for gdb using a gui. */
int (*ui_loop_hook) PARAMS ((int signo));
#endif
static SIM_DESC sd;
static RETSIGTYPE

15
sim/common/sim-core.c
View File

@ -29,13 +29,6 @@
#include "sim-hw.h"
#endif
#if (WITH_DEVICES)
/* TODO: create sim/common/device.h */
void device_error (device *me, char* message, ...);
int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, sim_cpu *processor, sim_cia cia);
#endif
/* "core" module install handler.
This is called via sim_module_install to install the "core"
@ -534,6 +527,7 @@ sim_core_read_buffer (SIM_DESC sd,
if (mapping->device != NULL)
{
int nr_bytes = len - count;
sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA;
if (raddr + nr_bytes - 1> mapping->bound)
nr_bytes = mapping->bound - raddr + 1;
if (device_io_read_buffer (mapping->device,
@ -541,8 +535,9 @@ sim_core_read_buffer (SIM_DESC sd,
mapping->space,
raddr,
nr_bytes,
sd,
cpu,
CIA_GET (cpu)) != nr_bytes)
cia) != nr_bytes)
break;
count += nr_bytes;
continue;
@ -599,6 +594,7 @@ sim_core_write_buffer (SIM_DESC sd,
&& mapping->device != NULL)
{
int nr_bytes = len - count;
sim_cia cia = cpu ? CIA_GET (cpu) : NULL_CIA;
if (raddr + nr_bytes - 1 > mapping->bound)
nr_bytes = mapping->bound - raddr + 1;
if (device_io_write_buffer (mapping->device,
@ -606,8 +602,9 @@ sim_core_write_buffer (SIM_DESC sd,
mapping->space,
raddr,
nr_bytes,
sd,
cpu,
CIA_GET(cpu)) != nr_bytes)
cia) != nr_bytes)
break;
count += nr_bytes;
continue;

9
sim/common/sim-core.h
View File

@ -340,4 +340,13 @@ DECLARE_SIM_CORE_READ_N(misaligned,7,8)
#undef DECLARE_SIM_CORE_READ_N
#if (WITH_DEVICES)
/* TODO: create sim/common/device.h */
/* These are defined with each particular cpu. */
void device_error (device *me, char* message, ...);
int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
#endif
#endif

21
sim/common/sim-events.c
View File

@ -39,15 +39,6 @@
#include <signal.h> /* For SIGPROCMASK et.al. */
#if __CYGWIN32__
/* The ui_loop_hook is called to keep the GUI alive while the simulator
is running. The counter is to make sure we do not wake it too often.
*/
extern void (*ui_loop_hook) PARAMS ((int));
static unsigned int ui_loop_hook_counter = 0;
#endif
typedef enum {
watch_invalid,
@ -1171,18 +1162,6 @@ sim_events_process (SIM_DESC sd)
/* this round of processing complete */
events->nr_ticks_to_process = 0;
#if __CYGWIN32__
/* Now call the ui_loop_hook to give the gui a chance to
process events. */
if (ui_loop_hook != NULL)
{
/* attempt to limit calls to 1-10 per second */
if (! (ui_loop_hook_counter++ & 0xf))
(*ui_loop_hook) (-2); /* magic */
}
#endif
}
#endif

16
sim/common/sim-io.c
View File

@ -33,6 +33,13 @@
#include <unistd.h>
#endif
/* Define the rate at which the simulator should poll the host
for a quit. */
#ifndef POLL_QUIT_INTERVAL
#define POLL_QUIT_INTERVAL 0x10
#endif
static int poll_quit_count = POLL_QUIT_INTERVAL;
/* See the file include/callbacks.h for a description */
@ -304,9 +311,12 @@ sim_io_error(SIM_DESC sd,
void
sim_io_poll_quit(SIM_DESC sd)
{
if (STATE_CALLBACK (sd)->poll_quit != NULL)
if (STATE_CALLBACK (sd)->poll_quit (STATE_CALLBACK (sd)))
sim_stop (sd);
if (STATE_CALLBACK (sd)->poll_quit != NULL && poll_quit_count-- < 0)
{
poll_quit_count = POLL_QUIT_INTERVAL;
if (STATE_CALLBACK (sd)->poll_quit (STATE_CALLBACK (sd)))
sim_stop (sd);
}
}

7
sim/common/sim-memopt.c
View File

@ -449,6 +449,10 @@ sim_memory_uninstall (SIM_DESC sd)
/* delete it and its aliases */
alias = *entry;
/* next victim */
*entry = (*entry)->next;
while (alias != NULL)
{
sim_memopt *dead = alias;
@ -456,9 +460,6 @@ sim_memory_uninstall (SIM_DESC sd)
sim_core_detach (sd, NULL, dead->level, dead->space, dead->addr);
zfree (dead);
}
/* next victim */
*entry = (*entry)->next;
}
}

3
sim/common/sim-model.h
View File

@ -79,6 +79,9 @@ typedef struct {
/* This is the argument to bfd_scan_arch. */
const char *bfd_name;
#define MACH_BFD_NAME(m) ((m)->bfd_name)
enum mach_attr num;
#define MACH_NUM(m) ((m)->num)
int word_bitsize;
#define MACH_WORD_BITSIZE(m) ((m)->word_bitsize)
int addr_bitsize;

4
sim/common/sim-n-core.h
View File

@ -167,7 +167,7 @@ sim_core_read_aligned_N(sim_cpu *cpu,
if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
{
unsigned_M data;
if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
if (device_io_read_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
device_error (mapping->device, "internal error - %s - io_read_buffer should not fail",
XSTRING (sim_core_read_aligned_N));
val = T2H_M (data);
@ -298,7 +298,7 @@ sim_core_write_aligned_N(sim_cpu *cpu,
if (WITH_CALLBACK_MEMORY && mapping->device != NULL)
{
unsigned_M data = H2T_M (val);
if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, cpu, cia) != N)
if (device_io_write_buffer (mapping->device, &data, mapping->space, addr, N, CPU_STATE (cpu), cpu, cia) != N)
device_error (mapping->device, "internal error - %s - io_write_buffer should not fail",
XSTRING (sim_core_write_aligned_N));
break;

28
sim/configure vendored
View File

@ -1413,6 +1413,7 @@ case "${target}" in
h8500-*-*) sim_target=h8500 ;;
i960-*-*) sim_target=i960 ;;
m32r-*-*) sim_target=m32r ;;
mcore-*-*) sim_target=mcore ;;
mips*-*-*)
# The MIPS simulator can only be compiled by gcc.
sim_target=mips
@ -1463,35 +1464,20 @@ case "${target}" in
z8k*-*-*) sim_target=z8k ;;
sparc64-*-*)
only_if_gcc=yes
if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then
sim_target=sparc
extra_subdirs="${extra_subdirs} testsuite"
else
sim_target=none # Don't build erc32 if sparc64.
fi
sim_target=none # Don't build erc32 if sparc64.
;;
sparclite*-*-* | sparc86x*-*-*)
# The SPARC simulator can only be compiled by gcc.
only_if_gcc=yes
if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then
sim_target=sparc
extra_subdirs="${extra_subdirs} testsuite"
else
sim_target=erc32
fi
sim_target=erc32
;;
sparc*-*-*)
# The SPARC simulator can only be compiled by gcc.
only_if_gcc=yes
if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then
sim_target=sparc
extra_subdirs="${extra_subdirs} testsuite"
else
# Unfortunately erc32 won't build on many hosts, so only enable
# it if the user really really wants it.
only_if_enabled=yes
sim_target=erc32
fi
# Unfortunately erc32 won't build on many hosts, so only enable
# it if the user really really wants it.
only_if_enabled=yes
sim_target=erc32
;;
*) sim_target=none ;;
esac

28
sim/configure.in
View File

@ -61,6 +61,7 @@ case "${target}" in
h8500-*-*) sim_target=h8500 ;;
i960-*-*) sim_target=i960 ;;
m32r-*-*) sim_target=m32r ;;
mcore-*-*) sim_target=mcore ;;
mips*-*-*)
# The MIPS simulator can only be compiled by gcc.
sim_target=mips
@ -111,35 +112,20 @@ case "${target}" in
z8k*-*-*) sim_target=z8k ;;
sparc64-*-*)
only_if_gcc=yes
if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then
sim_target=sparc
extra_subdirs="${extra_subdirs} testsuite"
else
sim_target=none # Don't build erc32 if sparc64.
fi
sim_target=none # Don't build erc32 if sparc64.
;;
sparclite*-*-* | sparc86x*-*-*)
# The SPARC simulator can only be compiled by gcc.
only_if_gcc=yes
if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then
sim_target=sparc
extra_subdirs="${extra_subdirs} testsuite"
else
sim_target=erc32
fi
sim_target=erc32
;;
sparc*-*-*)
# The SPARC simulator can only be compiled by gcc.
only_if_gcc=yes
if test "x${with_cgen}" = xyes -o "x${with_cgen_sim}" = xyes ; then
sim_target=sparc
extra_subdirs="${extra_subdirs} testsuite"
else
# Unfortunately erc32 won't build on many hosts, so only enable
# it if the user really really wants it.
only_if_enabled=yes
sim_target=erc32
fi
# Unfortunately erc32 won't build on many hosts, so only enable
# it if the user really really wants it.
only_if_enabled=yes
sim_target=erc32
;;
*) sim_target=none ;;
esac

21
sim/d10v/ChangeLog
View File

@ -1,3 +1,24 @@
1999-04-02 Keith Seitz <keiths@cygnus.com>
* interp.c (ui_loop_hook_counter): New global (when NEED_UI_LOOP_HOOK
defined).
(sim_resume): If the counter has expired, call the ui_loop_hook,
if defined.
(UI_LOOP_POLL_INTERVAL): Define. Used to tweak the frequency of
ui_loop_hook calls.
* Makefile.in (SIM_EXTRA_CFLAGS): Include NEED_UI_LOOP_HOOK.
Wed Mar 10 19:32:13 1999 Nick Clifton <nickc@cygnus.com>
* simops.c: If load instruction with auto increment/decrement
addressing is used when the destination register is the same as
the address register, then ignore the auto increment/decrement.
Wed Mar 10 19:32:13 1999 Martin M. Hunt <hunt@cygnus.com>
* simops.c (OP_5F00): Ifdef SYS_stat case because
not all systems have it defined.
1999-01-26 Jason Molenda (jsm@bugshack.cygnus.com)
* simops.c (OP_5607): Correct saturation comparison/assignment.

1
sim/d10v/Makefile.in
View File

@ -20,6 +20,7 @@
SIM_OBJS = interp.o table.o simops.o endian.o sim-load.o
SIM_EXTRA_CLEAN = clean-extra
SIM_EXTRA_CFLAGS = -DNEED_UI_LOOP_HOOK
INCLUDE = d10v_sim.h $(srcroot)/include/callback.h targ-vals.h endian.c

18
sim/d10v/interp.c
View File

@ -39,6 +39,17 @@ static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value)
extern void sim_set_profile PARAMS ((int n));
extern void sim_set_profile_size PARAMS ((int n));
#ifdef NEED_UI_LOOP_HOOK
/* How often to run the ui_loop update, when in use */
#define UI_LOOP_POLL_INTERVAL 0x14000
/* Counter for the ui_loop_hook update */
static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
/* Actual hook to call to run through gdb's gui event loop */
extern int (*ui_loop_hook) PARAMS ((int signo));
#endif /* NEED_UI_LOOP_HOOK */
#ifndef INLINE
#if defined(__GNUC__) && defined(__OPTIMIZE__)
#define INLINE __inline__
@ -784,6 +795,13 @@ sim_resume (sd, step, siggnal)
/* Writeback all the DATA / PC changes */
SLOT_FLUSH ();
#ifdef NEED_UI_LOOP_HOOK
if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
{
ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
ui_loop_hook (0);
}
#endif /* NEED_UI_LOOP_HOOK */
}
while ( !State.exception && !stop_simulator);

8
sim/d10v/simops.c
View File

@ -1333,7 +1333,8 @@ OP_6601 ()
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
INC_ADDR (OP[1], -4);
if (OP[0] != OP[1])
INC_ADDR (OP[1], -4);
trace_output_32 (tmp);
}
@ -1346,7 +1347,8 @@ OP_6201 ()
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
INC_ADDR (OP[1], 4);
if (OP[0] != OP[1])
INC_ADDR (OP[1], 4);
trace_output_32 (tmp);
}
@ -3124,6 +3126,7 @@ OP_5F00 ()
trace_output_void ();
break;
#ifdef TARGET_SYS_stat
case TARGET_SYS_stat:
trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
/* stat system call */
@ -3152,6 +3155,7 @@ OP_5F00 ()
}
trace_output_16 (result);
break;
#endif
case TARGET_SYS_chown:
trace_input ("<chown>", OP_R0, OP_R1, OP_R2);

13
sim/d30v/ChangeLog
View File

@ -1,3 +1,16 @@
1999-03-16 Martin Hunt <hunt@cygnus.com>
From Frank Ch. Eigler <fche@cygnus.com>
* cpu.h (mvtsys_left_p): New flag for MVTSYS instruction history.
* d30v-insns (mvtsys): Set this flag instead of left_kills_right_p.
(do_sath): Detect MVTSYS by new flag.
* engine.c (unqueue_writes): Detect MVTSYS by new flag.
(do_2_short, do_parallel): Initialize new flag.
1999-02-26 Frank Ch. Eigler <fche@cygnus.com>
* tconfig.in (SIM_HANDLES_LMA): Make it so.
1999-01-12 Frank Ch. Eigler <fche@cygnus.com>
* engine.c (unqueue_writes): Make PSW conflict resolution code

1
sim/d30v/cpu.h
View File

@ -115,6 +115,7 @@ struct _sim_cpu {
int trace_trap_p; /* If unknown traps dump out the regs */
int trace_action; /* trace bits at end of instructions */
int left_kills_right_p; /* left insn kills insn in right slot of -> */
int mvtsys_left_p; /* left insn was mvtsys */
int did_trap; /* we did a trap & need to finish it */
struct _write32 write32; /* queued up 32-bit writes */
struct _write64 write64; /* queued up 64-bit writes */

7
sim/d30v/d30v-insns
View File

@ -1520,11 +1520,11 @@ _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS
else
{
unsigned32 value = Rb;
CPU->mvtsys_left_p = 1;
if (CR == processor_status_word_cr)
{
unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */
value = ds | (value & PSW_VALID);
CPU->left_kills_right_p = 1;
}
else if (CR == backup_processor_status_word_cr
|| CR == debug_backup_processor_status_word_cr)
@ -1537,19 +1537,16 @@ _BRA,01110,00,6.CR,6.RB,6.ID:BRA:short:mu:MVTSYS
case 1: /* PSWL */
WRITE32_QUEUE_MASK (&PSW, EXTRACTED32(Rb, 16, 31),
PSW_VALID & 0x0000ffff);
CPU->left_kills_right_p = 1;
break;
case 2: /* PSWH */
{
unsigned32 ds = PSW & BIT32 (PSW_DS); /* preserve ds */
WRITE32_QUEUE_MASK (&PSW, (EXTRACTED32(Rb, 16, 31) << 16) | ds,
(PSW_VALID | ds) & 0xffff0000);
CPU->left_kills_right_p = 1;
}
break;
case 3: /* FLAG */
PSW_FLAG_SET_QUEUE(CR, Rb & 1);
CPU->left_kills_right_p = 1;
break;
default:
sim_engine_abort (SD, CPU, cia, "FIXME - illegal ID");
@ -1745,7 +1742,7 @@ void::function::do_sath:signed32 *ra, signed32 rb, signed32 src, int high, int u
if (updates_f4)
{
/* if MU instruction was a MVTSYS (lkr), unqueue register writes now */
if(STATE_CPU (sd, 0)->left_kills_right_p)
if(STATE_CPU (sd, 0)->mvtsys_left_p)
unqueue_writes (sd, STATE_CPU (sd, 0), cia);
PSW_FLAG_SET_QUEUE(PSW_S_FLAG, PSW_FLAG_VAL(PSW_S_FLAG) ^ (value & 1));
}

7
sim/d30v/engine.c
View File

@ -134,9 +134,9 @@ unqueue_writes (SIM_DESC sd,
if (ptr == psw_addr)
{
/* If MU instruction was not a MVTSYS (lkr), resolve PSW
/* If MU instruction was not a MVTSYS, resolve PSW
contention in favour of IU. */
if(! STATE_CPU (sd, 0)->left_kills_right_p)
if(! STATE_CPU (sd, 0)->mvtsys_left_p)
{
/* Detect contention in parallel writes to the same PSW flags.
The hardware allows the updates from IU to prevail over
@ -249,6 +249,7 @@ do_2_short (SIM_DESC sd,
/* run the first instruction */
STATE_CPU (sd, 0)->unit = unit;
STATE_CPU (sd, 0)->left_kills_right_p = 0;
STATE_CPU (sd, 0)->mvtsys_left_p = 0;
nia = s_idecode_issue(sd,
insn1,
cia);
@ -267,6 +268,7 @@ do_2_short (SIM_DESC sd,
}
STATE_CPU (sd, 0)->left_kills_right_p = 0;
STATE_CPU (sd, 0)->mvtsys_left_p = 0;
return nia;
}
@ -283,6 +285,7 @@ do_parallel (SIM_DESC sd,
/* run the first instruction */
STATE_CPU (sd, 0)->unit = memory_unit;
STATE_CPU (sd, 0)->left_kills_right_p = 0;
STATE_CPU (sd, 0)->mvtsys_left_p = 0;
nia_left = s_idecode_issue(sd,
left_insn,
cia);

4
sim/d30v/tconfig.in
View File

@ -2,3 +2,7 @@
/* Define this to enable the intrinsic breakpoint mechanism. */
#define SIM_HAVE_BREAKPOINTS
/* See sim-hload.c. We properly handle LMA. */
#define SIM_HANDLES_LMA 1

5
sim/erc32/ChangeLog
View File

@ -1,3 +1,8 @@
1999-03-03 DJ Delorie <dj@cygnus.com>
* configure.in: add termcap and -luser32 for host=cygwin
* configure: regenerate
1999-02-11 Hugo Tyson <hmt@cygnus.co.uk>
* exec.c (dispatch_instruction):

386
sim/erc32/configure vendored
View File

File diff suppressed because it is too large Load Diff

13
sim/erc32/configure.in
View File

@ -7,7 +7,18 @@ SIM_AC_COMMON
AC_CHECK_HEADERS(stdlib.h)
AC_CHECK_LIB(termcap, main, TERMCAP=-ltermcap, TERMCAP="")
# In the Cygwin environment, we need some additional flags.
AC_CACHE_CHECK([for cygwin], sim_cv_os_cygwin,
[AC_EGREP_CPP(lose, [
#ifdef __CYGWIN__
lose
#endif],[sim_cv_os_cygwin=yes],[sim_cv_os_cygwin=no])])
if test x$sim_cv_os_cygwin = xyes; then
TERMCAP='`if test -r ../../libtermcap/libtermcap.a; then echo ../../libtermcap/libtermcap.a; else echo -ltermcap; fi` -luser32'
else
AC_CHECK_LIB(termcap, main, TERMCAP=-ltermcap, TERMCAP="")
fi
AC_SUBST(TERMCAP)
SIM_AC_OUTPUT

41
sim/fr30/ChangeLog
View File

@ -1,3 +1,44 @@
Fri Apr 16 16:50:31 1999 Doug Evans <devans@charmed.cygnus.com>
* devices.c (device_io_read_buffer): New arg `sd'.
(device_io_write_buffer): New arg `sd'.
(device_error): Give proper arg spec.
1999-04-10 Doug Evans <devans@casey.cygnus.com>
* cpu.h,sem-switch.c,sem.c: Rebuild.
1999-03-27 Doug Evans <devans@casey.cygnus.com>
* decode.c: Rebuild.
1999-03-22 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,model.c: Rebuild.
* fr30.c (fr30bf_fetch_register): Replace calls to a_fr30_h_* with
calls to fr30bf_h_*.
(fr30bf_store_register): Ditto.
* traps.c (setup_int): Ditto.
* sim-if.c (sim_open): Update call to fr30_cgen_cpu_open.
Mon Mar 22 13:13:05 1999 Dave Brolley <brolley@cygnus.com>
* configure.in: Use SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT).
* configure: Regenerate.
* cpu.h: Regenerate.
1999-03-11 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,cpu.c,cpu.h: Rebuild.
* fr30-sim.h (GET_H_SBIT,SET_H_SBIT): Delete.
(GET_H_CCR,SET_H_CCR,GET_H_SCR,SET_H_SCR,GET_H_ILM,SET_H_ILM): Delete.
(GET_H_PS,SET_H_PS,GET_H_DR,SET_H_DR): Delete.
* sim-if.c (sim_open): Update call to fr30_cgen_cpu_open.
1999-02-25 Doug Evans <devans@casey.cygnus.com>
* cpu.h: Rebuild.
1999-02-09 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (SIM_EXTRA_DEPS): Add fr30-desc.h, delete cpu-opc.h.

660
sim/fr30/arch.c
View File

@ -33,663 +33,3 @@ const MACH *sim_machs[] =
0
};
/* Get the value of h-pc. */
USI
a_fr30_h_pc_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_pc_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-pc. */
void
a_fr30_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_pc_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-gr. */
SI
a_fr30_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
/* Set a value for h-gr. */
void
a_fr30_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-cr. */
SI
a_fr30_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_cr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
/* Set a value for h-cr. */
void
a_fr30_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_cr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-dr. */
SI
a_fr30_h_dr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_dr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
/* Set a value for h-dr. */
void
a_fr30_h_dr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_dr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-ps. */
USI
a_fr30_h_ps_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_ps_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-ps. */
void
a_fr30_h_ps_set (SIM_CPU *current_cpu, USI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_ps_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-r13. */
SI
a_fr30_h_r13_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_r13_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-r13. */
void
a_fr30_h_r13_set (SIM_CPU *current_cpu, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_r13_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-r14. */
SI
a_fr30_h_r14_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_r14_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-r14. */
void
a_fr30_h_r14_set (SIM_CPU *current_cpu, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_r14_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-r15. */
SI
a_fr30_h_r15_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_r15_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-r15. */
void
a_fr30_h_r15_set (SIM_CPU *current_cpu, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_r15_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-nbit. */
BI
a_fr30_h_nbit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_nbit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-nbit. */
void
a_fr30_h_nbit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_nbit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-zbit. */
BI
a_fr30_h_zbit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_zbit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-zbit. */
void
a_fr30_h_zbit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_zbit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-vbit. */
BI
a_fr30_h_vbit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_vbit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-vbit. */
void
a_fr30_h_vbit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_vbit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-cbit. */
BI
a_fr30_h_cbit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_cbit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-cbit. */
void
a_fr30_h_cbit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_cbit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-ibit. */
BI
a_fr30_h_ibit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_ibit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-ibit. */
void
a_fr30_h_ibit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_ibit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-sbit. */
BI
a_fr30_h_sbit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_sbit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-sbit. */
void
a_fr30_h_sbit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_sbit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-tbit. */
BI
a_fr30_h_tbit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_tbit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-tbit. */
void
a_fr30_h_tbit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_tbit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-d0bit. */
BI
a_fr30_h_d0bit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_d0bit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-d0bit. */
void
a_fr30_h_d0bit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_d0bit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-d1bit. */
BI
a_fr30_h_d1bit_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_d1bit_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-d1bit. */
void
a_fr30_h_d1bit_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_d1bit_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-ccr. */
UQI
a_fr30_h_ccr_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_ccr_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-ccr. */
void
a_fr30_h_ccr_set (SIM_CPU *current_cpu, UQI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_ccr_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-scr. */
UQI
a_fr30_h_scr_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_scr_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-scr. */
void
a_fr30_h_scr_set (SIM_CPU *current_cpu, UQI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_scr_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-ilm. */
UQI
a_fr30_h_ilm_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
return fr30bf_h_ilm_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-ilm. */
void
a_fr30_h_ilm_set (SIM_CPU *current_cpu, UQI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_FR30BF
case bfd_mach_fr30 :
fr30bf_h_ilm_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}

42
sim/fr30/arch.h
View File

@ -27,48 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define TARGET_BIG_ENDIAN 1
/* Cover fns for register access. */
USI a_fr30_h_pc_get (SIM_CPU *);
void a_fr30_h_pc_set (SIM_CPU *, USI);
SI a_fr30_h_gr_get (SIM_CPU *, UINT);
void a_fr30_h_gr_set (SIM_CPU *, UINT, SI);
SI a_fr30_h_cr_get (SIM_CPU *, UINT);
void a_fr30_h_cr_set (SIM_CPU *, UINT, SI);
SI a_fr30_h_dr_get (SIM_CPU *, UINT);
void a_fr30_h_dr_set (SIM_CPU *, UINT, SI);
USI a_fr30_h_ps_get (SIM_CPU *);
void a_fr30_h_ps_set (SIM_CPU *, USI);
SI a_fr30_h_r13_get (SIM_CPU *);
void a_fr30_h_r13_set (SIM_CPU *, SI);
SI a_fr30_h_r14_get (SIM_CPU *);
void a_fr30_h_r14_set (SIM_CPU *, SI);
SI a_fr30_h_r15_get (SIM_CPU *);
void a_fr30_h_r15_set (SIM_CPU *, SI);
BI a_fr30_h_nbit_get (SIM_CPU *);
void a_fr30_h_nbit_set (SIM_CPU *, BI);
BI a_fr30_h_zbit_get (SIM_CPU *);
void a_fr30_h_zbit_set (SIM_CPU *, BI);
BI a_fr30_h_vbit_get (SIM_CPU *);
void a_fr30_h_vbit_set (SIM_CPU *, BI);
BI a_fr30_h_cbit_get (SIM_CPU *);
void a_fr30_h_cbit_set (SIM_CPU *, BI);
BI a_fr30_h_ibit_get (SIM_CPU *);
void a_fr30_h_ibit_set (SIM_CPU *, BI);
BI a_fr30_h_sbit_get (SIM_CPU *);
void a_fr30_h_sbit_set (SIM_CPU *, BI);
BI a_fr30_h_tbit_get (SIM_CPU *);
void a_fr30_h_tbit_set (SIM_CPU *, BI);
BI a_fr30_h_d0bit_get (SIM_CPU *);
void a_fr30_h_d0bit_set (SIM_CPU *, BI);
BI a_fr30_h_d1bit_get (SIM_CPU *);
void a_fr30_h_d1bit_set (SIM_CPU *, BI);
UQI a_fr30_h_ccr_get (SIM_CPU *);
void a_fr30_h_ccr_set (SIM_CPU *, UQI);
UQI a_fr30_h_scr_get (SIM_CPU *);
void a_fr30_h_scr_set (SIM_CPU *, UQI);
UQI a_fr30_h_ilm_get (SIM_CPU *);
void a_fr30_h_ilm_set (SIM_CPU *, UQI);
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_FR30_1, MODEL_MAX

2
sim/fr30/configure vendored
View File

@ -3482,7 +3482,7 @@ else
fi
fi
wire_alignment="NONSTRICT_ALIGNMENT"
wire_alignment="FORCED_ALIGNMENT"
default_alignment=""
# Check whether --enable-sim-alignment or --disable-sim-alignment was given.

2
sim/fr30/configure.in
View File

@ -6,7 +6,7 @@ AC_INIT(Makefile.in)
SIM_AC_COMMON
SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
SIM_AC_OPTION_ALIGNMENT(FORCED_ALIGNMENT)
SIM_AC_OPTION_HOSTENDIAN
SIM_AC_OPTION_SCACHE(16384)
SIM_AC_OPTION_DEFAULT_MODEL(fr30-1)

1
sim/fr30/cpu.c
View File

@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define WANT_CPU_FR30BF
#include "sim-main.h"
#include "cgen-ops.h"
/* Get the value of h-pc. */

66
sim/fr30/cpu.h
View File

@ -50,21 +50,27 @@ typedef struct {
#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
/* dedicated registers */
SI h_dr[6];
/* GET_H_DR macro user-written */
/* SET_H_DR macro user-written */
/* program status */
#define GET_H_DR(index) fr30bf_h_dr_get_handler (current_cpu, index)
#define SET_H_DR(index, x) \
do { \
fr30bf_h_dr_set_handler (current_cpu, (index), (x));\
} while (0)
/* processor status */
USI h_ps;
/* GET_H_PS macro user-written */
/* SET_H_PS macro user-written */
/* General Register 13 explicitely required */
#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu)
#define SET_H_PS(x) \
do { \
fr30bf_h_ps_set_handler (current_cpu, (x));\
} while (0)
/* General Register 13 explicitly required */
SI h_r13;
#define GET_H_R13() CPU (h_r13)
#define SET_H_R13(x) (CPU (h_r13) = (x))
/* General Register 14 explicitely required */
/* General Register 14 explicitly required */
SI h_r14;
#define GET_H_R14() CPU (h_r14)
#define SET_H_R14(x) (CPU (h_r14) = (x))
/* General Register 15 explicitely required */
/* General Register 15 explicitly required */
SI h_r15;
#define GET_H_R15() CPU (h_r15)
#define SET_H_R15(x) (CPU (h_r15) = (x))
@ -88,10 +94,13 @@ typedef struct {
BI h_ibit;
#define GET_H_IBIT() CPU (h_ibit)
#define SET_H_IBIT(x) (CPU (h_ibit) = (x))
/* stack bit */
/* stack bit */
BI h_sbit;
/* GET_H_SBIT macro user-written */
/* SET_H_SBIT macro user-written */
#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu)
#define SET_H_SBIT(x) \
do { \
fr30bf_h_sbit_set_handler (current_cpu, (x));\
} while (0)
/* trace trap bit */
BI h_tbit;
#define GET_H_TBIT() CPU (h_tbit)
@ -104,18 +113,27 @@ typedef struct {
BI h_d1bit;
#define GET_H_D1BIT() CPU (h_d1bit)
#define SET_H_D1BIT(x) (CPU (h_d1bit) = (x))
/* condition code bits */
/* condition code bits */
UQI h_ccr;
/* GET_H_CCR macro user-written */
/* SET_H_CCR macro user-written */
#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu)
#define SET_H_CCR(x) \
do { \
fr30bf_h_ccr_set_handler (current_cpu, (x));\
} while (0)
/* system condition bits */
UQI h_scr;
/* GET_H_SCR macro user-written */
/* SET_H_SCR macro user-written */
/* interrupt level mask */
#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu)
#define SET_H_SCR(x) \
do { \
fr30bf_h_scr_set_handler (current_cpu, (x));\
} while (0)
/* interrupt level mask */
UQI h_ilm;
/* GET_H_ILM macro user-written */
/* SET_H_ILM macro user-written */
#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu)
#define SET_H_ILM(x) \
do { \
fr30bf_h_ilm_set_handler (current_cpu, (x));\
} while (0)
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} FR30BF_CPU_DATA;
@ -918,9 +936,9 @@ struct scache {
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
f_i20_4 = EXTRACT_UINT (insn, 16, 8, 4); \
f_i20_16 = (0|(EXTRACT_UINT (word_1, 16, 0, 16) << 0)); \
do {\
{\
f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\
} while (0);\
}\
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
@ -933,12 +951,14 @@ do {\
UINT f_Ri; \
/* Contents of trailing part of insn. */ \
UINT word_1; \
UINT word_2; \
unsigned int length;
#define EXTRACT_IFMT_LDI32_CODE \
length = 6; \
word_1 = GETIMEMUSI (current_cpu, pc + 2); \
word_1 = GETIMEMUHI (current_cpu, pc + 2); \
word_2 = GETIMEMUHI (current_cpu, pc + 4); \
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
f_i32 = (0|(EXTRACT_UINT (word_1, 32, 0, 32) << 0)); \
f_i32 = (0|(EXTRACT_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_UINT (word_1, 16, 0, 16) << 16)); \
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \

1239
sim/fr30/decode.c
View File

File diff suppressed because it is too large Load Diff

13
sim/fr30/devices.c
View File

@ -31,10 +31,8 @@ device fr30_devices;
int
device_io_read_buffer (device *me, void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_CPU *cpu, sim_cia cia)
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
SIM_DESC sd = CPU_STATE (cpu);
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
return nr_bytes;
@ -69,10 +67,8 @@ device_io_read_buffer (device *me, void *source, int space,
int
device_io_write_buffer (device *me, const void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_CPU *cpu, sim_cia cia)
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
SIM_DESC sd = CPU_STATE (cpu);
#if WITH_SCACHE
if (addr == MCCR_ADDR)
{
@ -96,4 +92,7 @@ device_io_write_buffer (device *me, const void *source, int space,
return nr_bytes;
}
void device_error () {}
void
device_error (device *me, char *message, ...)
{
}

12
sim/fr30/fr30-sim.h
View File

@ -33,33 +33,21 @@ with this program; if not, write to the Free Software Foundation, Inc.,
extern BI fr30bf_h_sbit_get_handler (SIM_CPU *);
extern void fr30bf_h_sbit_set_handler (SIM_CPU *, BI);
#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu)
#define SET_H_SBIT(val) fr30bf_h_sbit_set_handler (current_cpu, (val))
extern UQI fr30bf_h_ccr_get_handler (SIM_CPU *);
extern void fr30bf_h_ccr_set_handler (SIM_CPU *, UQI);
#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu)
#define SET_H_CCR(val) fr30bf_h_ccr_set_handler (current_cpu, (val))
extern UQI fr30bf_h_scr_get_handler (SIM_CPU *);
extern void fr30bf_h_scr_set_handler (SIM_CPU *, UQI);
#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu)
#define SET_H_SCR(val) fr30bf_h_scr_set_handler (current_cpu, (val))
extern UQI fr30bf_h_ilm_get_handler (SIM_CPU *);
extern void fr30bf_h_ilm_set_handler (SIM_CPU *, UQI);
#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu)
#define SET_H_ILM(val) fr30bf_h_ilm_set_handler (current_cpu, (val))
extern USI fr30bf_h_ps_get_handler (SIM_CPU *);
extern void fr30bf_h_ps_set_handler (SIM_CPU *, USI);
#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu)
#define SET_H_PS(val) fr30bf_h_ps_set_handler (current_cpu, (val))
extern SI fr30bf_h_dr_get_handler (SIM_CPU *, UINT);
extern void fr30bf_h_dr_set_handler (SIM_CPU *, UINT, SI);
#define GET_H_DR(regno) fr30bf_h_dr_get_handler (current_cpu, (regno))
#define SET_H_DR(regno, val) fr30bf_h_dr_set_handler (current_cpu, (regno), (val))
#define GETTWI GETTSI
#define SETTWI SETTSI

16
sim/fr30/fr30.c
View File

@ -48,15 +48,15 @@ int
fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
if (rn < 16)
SETTWI (buf, a_fr30_h_gr_get (current_cpu, rn));
SETTWI (buf, fr30bf_h_gr_get (current_cpu, rn));
else
switch (rn)
{
case PC_REGNUM :
SETTWI (buf, a_fr30_h_pc_get (current_cpu));
SETTWI (buf, fr30bf_h_pc_get (current_cpu));
break;
case PS_REGNUM :
SETTWI (buf, a_fr30_h_ps_get (current_cpu));
SETTWI (buf, fr30bf_h_ps_get (current_cpu));
break;
case TBR_REGNUM :
case RP_REGNUM :
@ -64,7 +64,7 @@ fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
case USP_REGNUM :
case MDH_REGNUM :
case MDL_REGNUM :
SETTWI (buf, a_fr30_h_dr_get (current_cpu,
SETTWI (buf, fr30bf_h_dr_get (current_cpu,
decode_gdb_dr_regnum (rn)));
break;
default :
@ -80,15 +80,15 @@ int
fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
if (rn < 16)
a_fr30_h_gr_set (current_cpu, rn, GETTWI (buf));
fr30bf_h_gr_set (current_cpu, rn, GETTWI (buf));
else
switch (rn)
{
case PC_REGNUM :
a_fr30_h_pc_set (current_cpu, GETTWI (buf));
fr30bf_h_pc_set (current_cpu, GETTWI (buf));
break;
case PS_REGNUM :
a_fr30_h_ps_set (current_cpu, GETTWI (buf));
fr30bf_h_ps_set (current_cpu, GETTWI (buf));
break;
case TBR_REGNUM :
case RP_REGNUM :
@ -96,7 +96,7 @@ fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
case USP_REGNUM :
case MDH_REGNUM :
case MDL_REGNUM :
a_fr30_h_dr_set (current_cpu,
fr30bf_h_dr_set (current_cpu,
decode_gdb_dr_regnum (rn),
GETTWI (buf));
break;

2
sim/fr30/model.c
View File

@ -3996,7 +3996,7 @@ fr30_init_cpu (SIM_CPU *cpu)
const MACH fr30_mach =
{
"fr30", "fr30",
"fr30", "fr30", MACH_FR30,
32, 32, & fr30_models[0], & fr30bf_imp_properties,
fr30_init_cpu,
fr30bf_prepare_run

624
sim/fr30/sem-switch.c
View File

File diff suppressed because it is too large Load Diff

624
sim/fr30/sem.c
View File

File diff suppressed because it is too large Load Diff

4
sim/fr30/sim-if.c
View File

@ -143,8 +143,8 @@ sim_open (kind, callback, abfd, argv)
/* Open a copy of the cpu descriptor table. */
{
CGEN_CPU_DESC cd = fr30_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
CGEN_ENDIAN_BIG);
CGEN_CPU_DESC cd = fr30_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
CGEN_ENDIAN_BIG);
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);

34
sim/fr30/traps.c
View File

@ -104,15 +104,15 @@ syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
static void
setup_int (SIM_CPU *current_cpu, PCADDR pc)
{
USI ssp = a_fr30_h_dr_get (current_cpu, H_DR_SSP);
USI ps = a_fr30_h_ps_get (current_cpu);
USI ssp = fr30bf_h_dr_get (current_cpu, H_DR_SSP);
USI ps = fr30bf_h_ps_get (current_cpu);
ssp -= 4;
SETMEMSI (current_cpu, pc, ssp, ps);
ssp -= 4;
SETMEMSI (current_cpu, pc, ssp, pc + 2);
a_fr30_h_dr_set (current_cpu, H_DR_SSP, ssp);
a_fr30_h_sbit_set (current_cpu, 0);
fr30bf_h_dr_set (current_cpu, H_DR_SSP, ssp);
fr30bf_h_sbit_set (current_cpu, 0);
}
/* Trap support.
@ -143,9 +143,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
We assume there's a branch there to some handler. */
USI new_pc;
setup_int (current_cpu, pc);
a_fr30_h_ibit_set (current_cpu, 0);
fr30bf_h_ibit_set (current_cpu, 0);
new_pc = GETMEMSI (current_cpu, pc,
a_fr30_h_dr_get (current_cpu, H_DR_TBR)
fr30bf_h_dr_get (current_cpu, H_DR_TBR)
+ 1024 - ((num + 1) * 4));
return new_pc;
}
@ -158,10 +158,10 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
CB_SYSCALL s;
CB_SYSCALL_INIT (&s);
s.func = a_fr30_h_gr_get (current_cpu, 0);
s.arg1 = a_fr30_h_gr_get (current_cpu, 4);
s.arg2 = a_fr30_h_gr_get (current_cpu, 5);
s.arg3 = a_fr30_h_gr_get (current_cpu, 6);
s.func = fr30bf_h_gr_get (current_cpu, 0);
s.arg1 = fr30bf_h_gr_get (current_cpu, 4);
s.arg2 = fr30bf_h_gr_get (current_cpu, 5);
s.arg3 = fr30bf_h_gr_get (current_cpu, 6);
if (s.func == TARGET_SYS_exit)
{
@ -173,9 +173,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
s.read_mem = syscall_read_mem;
s.write_mem = syscall_write_mem;
cb_syscall (cb, &s);
a_fr30_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */
a_fr30_h_gr_set (current_cpu, 4, s.result);
a_fr30_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */
fr30bf_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */
fr30bf_h_gr_set (current_cpu, 4, s.result);
fr30bf_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */
break;
}
@ -188,9 +188,9 @@ fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
{
USI new_pc;
setup_int (current_cpu, pc);
a_fr30_h_ibit_set (current_cpu, 0);
fr30bf_h_ibit_set (current_cpu, 0);
new_pc = GETMEMSI (current_cpu, pc,
a_fr30_h_dr_get (current_cpu, H_DR_TBR)
fr30bf_h_dr_get (current_cpu, H_DR_TBR)
+ 1024 - ((num + 1) * 4));
return new_pc;
}
@ -209,9 +209,9 @@ fr30_inte (SIM_CPU *current_cpu, PCADDR pc, int num)
We assume there's a branch there to some handler. */
USI new_pc;
setup_int (current_cpu, pc);
a_fr30_h_ilm_set (current_cpu, 4);
fr30bf_h_ilm_set (current_cpu, 4);
new_pc = GETMEMSI (current_cpu, pc,
a_fr30_h_dr_get (current_cpu, H_DR_TBR)
fr30bf_h_dr_get (current_cpu, H_DR_TBR)
+ 1024 - ((9 + 1) * 4));
return new_pc;
}

6
sim/h8300/ChangeLog
View File

@ -1,3 +1,9 @@
1999-04-02 Keith Seitz <keiths@cygnus.com>
* compile.c (POLL_QUIT_INTERVAL): Define. Used to tweak the
frequency at which the poll_quit callback is used.
(sim_resume): Use POLL_QUIT_INTERVAL instead of hard-coded value.
Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.

6
sim/h8300/compile.c
View File

@ -74,6 +74,10 @@ void sim_set_simcache_size PARAMS ((int));
#include "inst.h"
/* The rate at which to call the host's poll_quit callback. */
#define POLL_QUIT_INTERVAL 0x80000
#define LOW_BYTE(x) ((x) & 0xff)
#define HIGH_BYTE(x) (((x)>>8) & 0xff)
#define P(X,Y) ((X<<8) | Y)
@ -1726,7 +1730,7 @@ sim_resume (sd, step, siggnal)
if (--poll_count < 0)
{
poll_count = 100;
poll_count = POLL_QUIT_INTERVAL;
if ((*sim_callback->poll_quit) != NULL
&& (*sim_callback->poll_quit) (sim_callback))
sim_stop (sd);

48
sim/i960/ChangeLog
View File

@ -1,3 +1,51 @@
Fri Apr 16 16:50:31 1999 Doug Evans <devans@charmed.cygnus.com>
* devices.c (device_io_read_buffer): New arg `sd'.
(device_io_write_buffer): New arg `sd'.
(device_error): Give proper arg spec.
1999-04-14 Doug Evans <devans@casey.cygnus.com>
* i960-desc.c,i960-desc.h: Rebuild.
Sun Apr 11 00:25:17 1999 Jim Wilson <wilson@cygnus.com>
* TODO: Document more toolchain problems.
* cpu.h, decode.c, model.c, sem-switch.c, sem.c: Rebuild.
1999-04-10 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,sem-switch.c,sem.c: Rebuild.
Fri Apr 9 19:30:05 1999 Jim Wilson <wilson@cygnus.com>
* README, TODO: Clean up and update.
* sim-if.c: s/m32r/i960. s/sparc32/i960.
* decode.c, decode.h, i960-desc.c, i960-desc.h, i960-opc.h, model.c,
sem-switch.c, sem.c: Rebuild.
1999-03-27 Doug Evans <devans@casey.cygnus.com>
* decode.c: Rebuild.
1999-03-22 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,model.c,i960-desc.c,i960-desc.h,i960-opc.h: Rebuild.
* i960-sim.h (a_i960_h_gr_get,a_i960_h_gr_set): Declare.
(a_i960_h_pc_get,a_i960_h_pc_set): Declare.
* i960.c (a_i960_h_gr_get,a_i960_h_gr_set): New functions.
(a_i960_h_pc_get,a_i960_h_pc_set): Ditto.
* sim-if.c (sim_open): Update call to i960_cgen_cpu_open.
1999-03-11 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,cpu.c,i960-desc.c,i960-desc.h: Rebuild.
* sim-if.c (sim_open): Update call to i960_cgen_cpu_open.
1999-02-25 Doug Evans <devans@casey.cygnus.com>
* i960-desc.c,i960-desc.h: Rebuild.
1999-02-09 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (I960_OBJS): Add i960-desc.o.

11
sim/i960/README
View File

@ -1,9 +1,18 @@
This is the i960 simulator directory.
It is still work-in-progress. The current sources are reasonably
It is still a work in progress. The current sources are reasonably
well tested and lots of features are in. However, there's lots
more yet to come.
---
The simulator only supports the i960KA currently. Not all instructions
are supported yet, only those instructions needed by the gcc/g++ testsuites
have been added so far. There is no profiling support as yet. There is
no pipeline or timing support as yet.
---
There are lots of machine generated files in the source directory!
They are only generated if you configure with --enable-cgen-maint,
similar in behaviour to Makefile.in, configure under automake/autoconf.

73
sim/i960/TODO
View File

@ -1,9 +1,64 @@
- header file dependencies revisit
- hooks cleanup
- testsuites
- FIXME's
- memory accesses still test if profiling is on even in fast mode
- fill nop counting done even in fast mode
- have semantic code use G/SET_H_FOO if not default [incl fun-access]
- have G/SET_H_FOO macros call function if fun-access
- --> can always use G/S_H_FOO macros
See ??? comments here and in cgen, and in libgloss/i960.
Simulator:
Update sim/i960 directory from sim/m32r directory. sim/i960 dir was created
by copying the sim/m32r in September 1998, and is missing all sim/m32r updates
since then.
Review, clean up, finish, etc simulator files that are not cgen generated.
This includes devices.c, i960-sim.h, mloop.in, sim-if.c, sim-main.h,
tconfig.in, and traps.c.
Some functions do not show up in trace output. This occasionally happens
for main.
Gdb core dumps if compile without -mka. Apparently a problem with recognizing
"core" machine type.
Get profiling working.
Add pipelining, execution unit, timing, etc info.
Add support for other models, besides KA.
Add support for newer architectures, e.g. v1.1 instructions.
Compiler:
Running gcc gives nm warning from collect about missing a.out file.
The output file is b.out, not a.out. Collect is probably looking for
the wrong file name.
Use of -mca gives lots of linker warnings for ka/ca architecture conflicts,
but the two architectures are compatible.
Need 96 bit long double support in fp-bit.c, otherwise any testcase using
long double arithmetic hits an abort and runtime.
Compiler takes far too much time to compile PlumHall testcases at high
optimization levels.
r2 seems to be an available call-clobbered registers, since it isn't used
until a call occurs, and is dead when the call returns.
BSP:
Libgloss does not check for syscall error returns, which means errno never
gets set.
Libgloss does not use the syscall.h file.
Binutils:
Objdump -d fails on 64-bit host, specifically irix6.
Gdb:
Gdb sometimes prints messages about trace/breakpoint trap when hitting a
breakpoint.
Frame, up, down and related commands don't work.
Gdb fails when next'ing over a leaf function compiled with -mleaf-procedure.
Gdb fails when step'ing over a return from such a leaf function.

126
sim/i960/arch.c
View File

@ -36,129 +36,3 @@ const MACH *sim_machs[] =
0
};
/* Get the value of h-pc. */
USI
a_i960_h_pc_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ka_sa :
return i960base_h_pc_get (current_cpu);
#endif
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ca :
return i960base_h_pc_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-pc. */
void
a_i960_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ka_sa :
i960base_h_pc_set (current_cpu, newval);
break;
#endif
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ca :
i960base_h_pc_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-gr. */
SI
a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ka_sa :
return i960base_h_gr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ca :
return i960base_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
/* Set a value for h-gr. */
void
a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ka_sa :
i960base_h_gr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ca :
i960base_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-cc. */
SI
a_i960_h_cc_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ka_sa :
return i960base_h_cc_get (current_cpu);
#endif
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ca :
return i960base_h_cc_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-cc. */
void
a_i960_h_cc_set (SIM_CPU *current_cpu, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ka_sa :
i960base_h_cc_set (current_cpu, newval);
break;
#endif
#ifdef HAVE_CPU_I960BASE
case bfd_mach_i960_ca :
i960base_h_cc_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}

8
sim/i960/arch.h
View File

@ -27,14 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define TARGET_BIG_ENDIAN 1
/* Cover fns for register access. */
USI a_i960_h_pc_get (SIM_CPU *);
void a_i960_h_pc_set (SIM_CPU *, USI);
SI a_i960_h_gr_get (SIM_CPU *, UINT);
void a_i960_h_gr_set (SIM_CPU *, UINT, SI);
SI a_i960_h_cc_get (SIM_CPU *);
void a_i960_h_cc_set (SIM_CPU *, SI);
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_I960KA, MODEL_I960CA, MODEL_MAX

1
sim/i960/cpu.c
View File

@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define WANT_CPU_I960BASE
#include "sim-main.h"
#include "cgen-ops.h"
/* Get the value of h-pc. */

264
sim/i960/cpu.h
View File

@ -154,6 +154,34 @@ union sem_fields {
SI * i_dst;
unsigned char out_dst;
} fmt_not3;
struct { /* e.g. shlo $src1, $src2, $dst */
SI * i_src1;
SI * i_src2;
SI * i_dst;
unsigned char in_src1;
unsigned char in_src2;
unsigned char out_dst;
} fmt_shlo;
struct { /* e.g. shlo $lit1, $src2, $dst */
UINT f_src1;
SI * i_src2;
SI * i_dst;
unsigned char in_src2;
unsigned char out_dst;
} fmt_shlo1;
struct { /* e.g. shlo $src1, $lit2, $dst */
UINT f_src2;
SI * i_src1;
SI * i_dst;
unsigned char in_src1;
unsigned char out_dst;
} fmt_shlo2;
struct { /* e.g. shlo $lit1, $lit2, $dst */
UINT f_src1;
UINT f_src2;
SI * i_dst;
unsigned char out_dst;
} fmt_shlo3;
struct { /* e.g. emul $src1, $src2, $dst */
UINT f_srcdst;
SI * i_src1;
@ -162,7 +190,7 @@ union sem_fields {
unsigned char in_src1;
unsigned char in_src2;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul;
struct { /* e.g. emul $lit1, $src2, $dst */
UINT f_srcdst;
@ -171,7 +199,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_src2;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul1;
struct { /* e.g. emul $src1, $lit2, $dst */
UINT f_srcdst;
@ -180,7 +208,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_src1;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul2;
struct { /* e.g. emul $lit1, $lit2, $dst */
UINT f_srcdst;
@ -188,67 +216,67 @@ union sem_fields {
UINT f_src2;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_emul3;
struct { /* e.g. movl $src1, $dst */
UINT f_src1;
UINT f_srcdst;
SI * i_src1;
SI * i_dst;
unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_src1_1;
unsigned char in_src1;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_movl;
struct { /* e.g. movl $lit1, $dst */
UINT f_srcdst;
UINT f_src1;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_movl1;
struct { /* e.g. movt $src1, $dst */
UINT f_src1;
UINT f_srcdst;
SI * i_src1;
SI * i_dst;
unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_src1_1;
unsigned char in_h_gr_add__VM_index_of_src1_2;
unsigned char in_src1;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_movt;
struct { /* e.g. movt $lit1, $dst */
UINT f_srcdst;
UINT f_src1;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_movt1;
struct { /* e.g. movq $src1, $dst */
UINT f_src1;
UINT f_srcdst;
SI * i_src1;
SI * i_dst;
unsigned char in_h_gr_add__VM_index_of_src1_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_src1_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_src1_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_src1_1;
unsigned char in_h_gr_add__VM_index_of_src1_2;
unsigned char in_h_gr_add__VM_index_of_src1_3;
unsigned char in_src1;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_movq;
struct { /* e.g. movq $lit1, $dst */
UINT f_srcdst;
UINT f_src1;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_movq1;
struct { /* e.g. modpc $src1, $src2, $dst */
SI * i_src2;
@ -603,7 +631,7 @@ union sem_fields {
UINT f_offset;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_offset;
struct { /* e.g. ldl $offset($abase), $dst */
UINT f_srcdst;
@ -612,7 +640,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_offset;
struct { /* e.g. ldl ($abase), $dst */
UINT f_srcdst;
@ -620,7 +648,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect;
struct { /* e.g. ldl ($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@ -631,14 +659,14 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_index;
struct { /* e.g. ldl $optdisp, $dst */
UINT f_srcdst;
UINT f_optdisp;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_disp;
struct { /* e.g. ldl $optdisp($abase), $dst */
UINT f_srcdst;
@ -647,7 +675,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_disp;
struct { /* e.g. ldl $optdisp[$index*S$scale], $dst */
UINT f_srcdst;
@ -657,7 +685,7 @@ union sem_fields {
SI * i_dst;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_index_disp;
struct { /* e.g. ldl $optdisp($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@ -669,15 +697,15 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_1;
} fmt_ldl_indirect_index_disp;
struct { /* e.g. ldt $offset, $dst */
UINT f_srcdst;
UINT f_offset;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_offset;
struct { /* e.g. ldt $offset($abase), $dst */
UINT f_srcdst;
@ -686,8 +714,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_offset;
struct { /* e.g. ldt ($abase), $dst */
UINT f_srcdst;
@ -695,8 +723,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect;
struct { /* e.g. ldt ($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@ -707,16 +735,16 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_index;
struct { /* e.g. ldt $optdisp, $dst */
UINT f_srcdst;
UINT f_optdisp;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_disp;
struct { /* e.g. ldt $optdisp($abase), $dst */
UINT f_srcdst;
@ -725,8 +753,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_disp;
struct { /* e.g. ldt $optdisp[$index*S$scale], $dst */
UINT f_srcdst;
@ -736,8 +764,8 @@ union sem_fields {
SI * i_dst;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_index_disp;
struct { /* e.g. ldt $optdisp($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@ -749,17 +777,17 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
} fmt_ldt_indirect_index_disp;
struct { /* e.g. ldq $offset, $dst */
UINT f_srcdst;
UINT f_offset;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_offset;
struct { /* e.g. ldq $offset($abase), $dst */
UINT f_srcdst;
@ -768,9 +796,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_offset;
struct { /* e.g. ldq ($abase), $dst */
UINT f_srcdst;
@ -778,9 +806,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect;
struct { /* e.g. ldq ($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@ -791,18 +819,18 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_index;
struct { /* e.g. ldq $optdisp, $dst */
UINT f_srcdst;
UINT f_optdisp;
SI * i_dst;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_disp;
struct { /* e.g. ldq $optdisp($abase), $dst */
UINT f_srcdst;
@ -811,9 +839,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_disp;
struct { /* e.g. ldq $optdisp[$index*S$scale], $dst */
UINT f_srcdst;
@ -823,9 +851,9 @@ union sem_fields {
SI * i_dst;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_index_disp;
struct { /* e.g. ldq $optdisp($abase)[$index*S$scale], $dst */
UINT f_srcdst;
@ -837,9 +865,9 @@ union sem_fields {
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_1;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_2;
unsigned char out_h_gr_add__VM_index_of_dst_const__WI_3;
unsigned char out_h_gr_add__VM_index_of_dst_1;
unsigned char out_h_gr_add__VM_index_of_dst_2;
unsigned char out_h_gr_add__VM_index_of_dst_3;
} fmt_ldq_indirect_index_disp;
struct { /* e.g. st $st_src, $offset */
UINT f_offset;
@ -1016,7 +1044,7 @@ union sem_fields {
UINT f_srcdst;
UINT f_offset;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_offset;
struct { /* e.g. stl $st_src, $offset($abase) */
@ -1025,7 +1053,7 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_indirect_offset;
struct { /* e.g. stl $st_src, ($abase) */
@ -1033,7 +1061,7 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_indirect;
struct { /* e.g. stl $st_src, ($abase)[$index*S$scale] */
@ -1043,7 +1071,7 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stl_indirect_index;
@ -1051,7 +1079,7 @@ union sem_fields {
UINT f_srcdst;
UINT f_optdisp;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_disp;
struct { /* e.g. stl $st_src, $optdisp($abase) */
@ -1060,7 +1088,7 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_st_src;
} fmt_stl_indirect_disp;
struct { /* e.g. stl $st_src, $optdisp[$index*S$scale */
@ -1069,7 +1097,7 @@ union sem_fields {
UINT f_scale;
SI * i_index;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stl_index_disp;
@ -1081,7 +1109,7 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stl_indirect_index_disp;
@ -1089,8 +1117,8 @@ union sem_fields {
UINT f_srcdst;
UINT f_offset;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_offset;
struct { /* e.g. stt $st_src, $offset($abase) */
@ -1099,8 +1127,8 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_indirect_offset;
struct { /* e.g. stt $st_src, ($abase) */
@ -1108,8 +1136,8 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_indirect;
struct { /* e.g. stt $st_src, ($abase)[$index*S$scale] */
@ -1119,8 +1147,8 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stt_indirect_index;
@ -1128,8 +1156,8 @@ union sem_fields {
UINT f_srcdst;
UINT f_optdisp;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_disp;
struct { /* e.g. stt $st_src, $optdisp($abase) */
@ -1138,8 +1166,8 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_st_src;
} fmt_stt_indirect_disp;
struct { /* e.g. stt $st_src, $optdisp[$index*S$scale */
@ -1148,8 +1176,8 @@ union sem_fields {
UINT f_scale;
SI * i_index;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stt_index_disp;
@ -1161,8 +1189,8 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stt_indirect_index_disp;
@ -1170,9 +1198,9 @@ union sem_fields {
UINT f_srcdst;
UINT f_offset;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_offset;
struct { /* e.g. stq $st_src, $offset($abase) */
@ -1181,9 +1209,9 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_indirect_offset;
struct { /* e.g. stq $st_src, ($abase) */
@ -1191,9 +1219,9 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_indirect;
struct { /* e.g. stq $st_src, ($abase)[$index*S$scale] */
@ -1203,9 +1231,9 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stq_indirect_index;
@ -1213,9 +1241,9 @@ union sem_fields {
UINT f_srcdst;
UINT f_optdisp;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_disp;
struct { /* e.g. stq $st_src, $optdisp($abase) */
@ -1224,9 +1252,9 @@ union sem_fields {
SI * i_abase;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_st_src;
} fmt_stq_indirect_disp;
struct { /* e.g. stq $st_src, $optdisp[$index*S$scale */
@ -1235,9 +1263,9 @@ union sem_fields {
UINT f_scale;
SI * i_index;
SI * i_st_src;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stq_index_disp;
@ -1249,9 +1277,9 @@ union sem_fields {
SI * i_index;
SI * i_st_src;
unsigned char in_abase;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_1;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_2;
unsigned char in_h_gr_add__VM_index_of_st_src_const__WI_3;
unsigned char in_h_gr_add__VM_index_of_st_src_1;
unsigned char in_h_gr_add__VM_index_of_st_src_2;
unsigned char in_h_gr_add__VM_index_of_st_src_3;
unsigned char in_index;
unsigned char in_st_src;
} fmt_stq_indirect_index_disp;

3656
sim/i960/decode.c
View File

File diff suppressed because it is too large Load Diff

14
sim/i960/decode.h
View File

@ -48,8 +48,10 @@ typedef enum i960base_insn_type {
, I960BASE_INSN_NOTAND2, I960BASE_INSN_NOTAND3, I960BASE_INSN_XOR, I960BASE_INSN_XOR1
, I960BASE_INSN_XOR2, I960BASE_INSN_XOR3, I960BASE_INSN_OR, I960BASE_INSN_OR1
, I960BASE_INSN_OR2, I960BASE_INSN_OR3, I960BASE_INSN_NOR, I960BASE_INSN_NOR1
, I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1
, I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1
, I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_XNOR, I960BASE_INSN_XNOR1
, I960BASE_INSN_XNOR2, I960BASE_INSN_XNOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1
, I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_ORNOT, I960BASE_INSN_ORNOT1
, I960BASE_INSN_ORNOT2, I960BASE_INSN_ORNOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1
, I960BASE_INSN_CLRBIT2, I960BASE_INSN_CLRBIT3, I960BASE_INSN_SHLO, I960BASE_INSN_SHLO1
, I960BASE_INSN_SHLO2, I960BASE_INSN_SHLO3, I960BASE_INSN_SHRO, I960BASE_INSN_SHRO1
, I960BASE_INSN_SHRO2, I960BASE_INSN_SHRO3, I960BASE_INSN_SHLI, I960BASE_INSN_SHLI1
@ -192,10 +194,18 @@ SEM (nor)
SEM (nor1)
SEM (nor2)
SEM (nor3)
SEM (xnor)
SEM (xnor1)
SEM (xnor2)
SEM (xnor3)
SEM (not)
SEM (not1)
SEM (not2)
SEM (not3)
SEM (ornot)
SEM (ornot1)
SEM (ornot2)
SEM (ornot3)
SEM (clrbit)
SEM (clrbit1)
SEM (clrbit2)

13
sim/i960/devices.c
View File

@ -32,10 +32,8 @@ device i960_devices;
int
device_io_read_buffer (device *me, void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_CPU *cpu, sim_cia cia)
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
SIM_DESC sd = CPU_STATE (cpu);
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
return nr_bytes;
@ -70,10 +68,8 @@ device_io_read_buffer (device *me, void *source, int space,
int
device_io_write_buffer (device *me, const void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_CPU *cpu, sim_cia cia)
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
SIM_DESC sd = CPU_STATE (cpu);
#if WITH_SCACHE
/* MSPR support is deprecated but is kept in for upward compatibility
with existing overlay support. */
@ -105,4 +101,7 @@ device_io_write_buffer (device *me, const void *source, int space,
return nr_bytes;
}
void device_error () {}
void
device_error (device *me, char *message, ...)
{
}

1087
sim/i960/i960-desc.c
View File

File diff suppressed because it is too large Load Diff

101
sim/i960/i960-desc.h
View File

@ -34,15 +34,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define HAVE_CPU_I960BASE
#define CGEN_INSN_LSB0_P 0
#define CGEN_WORD_BITSIZE 32
#define CGEN_DEFAULT_INSN_BITSIZE 32
#define CGEN_BASE_INSN_BITSIZE 32
#define CGEN_MIN_INSN_BITSIZE 32
#define CGEN_MAX_INSN_BITSIZE 64
#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8)
#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
/* Maximum size of any insn (in bytes). */
#define CGEN_MAX_INSN_SIZE 8
#define CGEN_INT_INSN_P 0
/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
@ -193,24 +188,6 @@ typedef enum insn_ctrl_zero {
CTRL_ZERO_0
} INSN_CTRL_ZERO;
/* Enum declaration for general registers. */
typedef enum h_gr {
H_GR_FP = 31, H_GR_SP = 1, H_GR_R0 = 0, H_GR_R1 = 1
, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
, H_GR_R14 = 14, H_GR_R15 = 15, H_GR_G0 = 16, H_GR_G1 = 17
, H_GR_G2 = 18, H_GR_G3 = 19, H_GR_G4 = 20, H_GR_G5 = 21
, H_GR_G6 = 22, H_GR_G7 = 23, H_GR_G8 = 24, H_GR_G9 = 25
, H_GR_G10 = 26, H_GR_G11 = 27, H_GR_G12 = 28, H_GR_G13 = 29
, H_GR_G14 = 30, H_GR_G15 = 31
} H_GR;
/* Enum declaration for condition code. */
typedef enum h_cc {
H_CC_CC
} H_CC;
/* Attributes. */
/* Enum declaration for machine type selection. */
@ -218,7 +195,13 @@ typedef enum mach_attr {
MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
ISA_I960, ISA_MAX
} ISA_ATTR;
/* Number of architecture variants. */
#define MAX_ISAS 1
#define MAX_MACHS ((int) MACH_MAX)
/* Ifield support. */
@ -229,13 +212,13 @@ extern const struct cgen_ifld i960_cgen_ifld_table[];
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
CGEN_IFLD_MACH, CGEN_IFLD_NBOOLS, CGEN_IFLD_START_BOOL = 31, CGEN_IFLD_VIRTUAL
, CGEN_IFLD_UNSIGNED, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
, CGEN_IFLD_SIGN_OPT
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;
/* Number of non-boolean elements in cgen_ifld. */
#define CGEN_IFLD_NBOOL_ATTRS ((int) CGEN_IFLD_NBOOLS)
/* Number of non-boolean elements in cgen_ifld_attr. */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
/* Enum declaration for i960 ifield types. */
typedef enum ifield_type {
@ -254,20 +237,19 @@ typedef enum ifield_type {
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
CGEN_HW_MACH, CGEN_HW_NBOOLS, CGEN_HW_START_BOOL = 31, CGEN_HW_VIRTUAL
, CGEN_HW_UNSIGNED, CGEN_HW_SIGNED, CGEN_HW_CACHE_ADDR, CGEN_HW_FUN_ACCESS
, CGEN_HW_PC, CGEN_HW_PROFILE
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;
/* Number of non-boolean elements in cgen_hw. */
#define CGEN_HW_NBOOL_ATTRS ((int) CGEN_HW_NBOOLS)
/* Number of non-boolean elements in cgen_hw_attr. */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
/* Enum declaration for i960 hardware types. */
typedef enum hw_type {
HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
, HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CC
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CC
, HW_MAX
} HW_TYPE;
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@ -275,13 +257,13 @@ typedef enum hw_type {
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
CGEN_OPERAND_MACH, CGEN_OPERAND_NBOOLS, CGEN_OPERAND_START_BOOL = 31, CGEN_OPERAND_VIRTUAL
, CGEN_OPERAND_UNSIGNED, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand. */
#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_NBOOLS)
/* Number of non-boolean elements in cgen_operand_attr. */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
/* Enum declaration for i960 operand types. */
typedef enum cgen_operand_type {
@ -302,20 +284,21 @@ typedef enum cgen_operand_type {
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
CGEN_INSN_MACH, CGEN_INSN_NBOOLS, CGEN_INSN_START_BOOL = 31, CGEN_INSN_ALIAS
, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI
, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX, CGEN_INSN_NO_DIS
, CGEN_INSN_PBB
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn. */
#define CGEN_INSN_NBOOL_ATTRS ((int) CGEN_INSN_NBOOLS)
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
/* Attributes. */
extern const CGEN_ATTR_TABLE i960_cgen_hw_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
@ -324,18 +307,6 @@ extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
extern CGEN_KEYWORD i960_cgen_opval_h_gr;
extern CGEN_KEYWORD i960_cgen_opval_h_cc;
#define CGEN_INIT_PARSE(od) \
{\
}
#define CGEN_INIT_INSERT(od) \
{\
}
#define CGEN_INIT_EXTRACT(od) \
{\
}
#define CGEN_INIT_PRINT(od) \
{\
}

18
sim/i960/i960-opc.h
View File

@ -54,8 +54,10 @@ typedef enum cgen_insn_type {
, I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2
, I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2
, I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2
, I960_INSN_NOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2
, I960_INSN_NOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2
, I960_INSN_NOR3, I960_INSN_XNOR, I960_INSN_XNOR1, I960_INSN_XNOR2
, I960_INSN_XNOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2
, I960_INSN_NOT3, I960_INSN_ORNOT, I960_INSN_ORNOT1, I960_INSN_ORNOT2
, I960_INSN_ORNOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2
, I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2
, I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2
, I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2
@ -151,6 +153,18 @@ struct cgen_fields
long f_ctrl_zero;
};
#define CGEN_INIT_PARSE(od) \
{\
}
#define CGEN_INIT_INSERT(od) \
{\
}
#define CGEN_INIT_EXTRACT(od) \
{\
}
#define CGEN_INIT_PRINT(od) \
{\
}
#endif /* I960_OPC_H */

5
sim/i960/i960-sim.h
View File

@ -10,6 +10,11 @@
#define FP0_REGNUM 36 /* First floating point register */
/* Some registers have more than one name */
#define PC_REGNUM IP_REGNUM /* GDB refers to ip as the Program Counter */
SI a_i960_h_gr_get (SIM_CPU *, UINT);
void a_i960_h_gr_set (SIM_CPU *, UINT, SI);
IADDR a_i960_h_pc_get (SIM_CPU *);
void a_i960_h_pc_set (SIM_CPU *, IADDR);
#define GETTWI GETTSI
#define SETTWI SETTSI

64
sim/i960/i960.c
View File

@ -68,6 +68,70 @@ i960base_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
return -1; /*FIXME*/
}
/* Cover fns for mach independent register accesses. */
SI
a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
return i960base_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
i960base_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
IADDR
a_i960_h_pc_get (SIM_CPU *current_cpu)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
return i960base_h_pc_get (current_cpu);
#endif
default :
abort ();
}
}
void
a_i960_h_pc_set (SIM_CPU *current_cpu, IADDR newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
i960base_h_pc_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
#if WITH_PROFILE_MODEL_P
/* FIXME: Some of these should be inline or macros. Later. */

340
sim/i960/model.c
View File

@ -994,6 +994,70 @@ model_i960KA_nor3 (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_i960KA_xnor (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_xnor1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_xnor2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_xnor3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_not (SIM_CPU *current_cpu, void *sem_arg)
{
@ -1058,6 +1122,70 @@ model_i960KA_not3 (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_i960KA_ornot (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_ornot1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_ornot2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_ornot3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960KA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960KA_clrbit (SIM_CPU *current_cpu, void *sem_arg)
{
@ -1125,7 +1253,7 @@ model_i960KA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1141,7 +1269,7 @@ model_i960KA_shlo (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1157,7 +1285,7 @@ model_i960KA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1173,7 +1301,7 @@ model_i960KA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1189,7 +1317,7 @@ model_i960KA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1205,7 +1333,7 @@ model_i960KA_shro (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1221,7 +1349,7 @@ model_i960KA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1237,7 +1365,7 @@ model_i960KA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1253,7 +1381,7 @@ model_i960KA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1269,7 +1397,7 @@ model_i960KA_shli (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1285,7 +1413,7 @@ model_i960KA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1301,7 +1429,7 @@ model_i960KA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1317,7 +1445,7 @@ model_i960KA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1333,7 +1461,7 @@ model_i960KA_shri (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1349,7 +1477,7 @@ model_i960KA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -1365,7 +1493,7 @@ model_i960KA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960KA_shri3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5522,6 +5650,70 @@ model_i960CA_nor3 (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_i960CA_xnor (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_xnor1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_xnor2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_xnor3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_not (SIM_CPU *current_cpu, void *sem_arg)
{
@ -5586,6 +5778,70 @@ model_i960CA_not3 (SIM_CPU *current_cpu, void *sem_arg)
#undef FLD
}
static int
model_i960CA_ornot (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_ornot1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_ornot2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_ornot3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_mulo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += i960base_model_i960CA_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
model_i960CA_clrbit (SIM_CPU *current_cpu, void *sem_arg)
{
@ -5653,7 +5909,7 @@ model_i960CA_clrbit3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5669,7 +5925,7 @@ model_i960CA_shlo (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5685,7 +5941,7 @@ model_i960CA_shlo1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5701,7 +5957,7 @@ model_i960CA_shlo2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5717,7 +5973,7 @@ model_i960CA_shlo3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5733,7 +5989,7 @@ model_i960CA_shro (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5749,7 +6005,7 @@ model_i960CA_shro1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5765,7 +6021,7 @@ model_i960CA_shro2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5781,7 +6037,7 @@ model_i960CA_shro3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5797,7 +6053,7 @@ model_i960CA_shli (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5813,7 +6069,7 @@ model_i960CA_shli1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5829,7 +6085,7 @@ model_i960CA_shli2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5845,7 +6101,7 @@ model_i960CA_shli3 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit.f
#define FLD(f) abuf->fields.fmt_shlo.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5861,7 +6117,7 @@ model_i960CA_shri (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit1.f
#define FLD(f) abuf->fields.fmt_shlo1.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5877,7 +6133,7 @@ model_i960CA_shri1 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit2.f
#define FLD(f) abuf->fields.fmt_shlo2.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -5893,7 +6149,7 @@ model_i960CA_shri2 (SIM_CPU *current_cpu, void *sem_arg)
static int
model_i960CA_shri3 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_notbit3.f
#define FLD(f) abuf->fields.fmt_shlo3.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@ -9162,10 +9418,18 @@ static const INSN_TIMING i960KA_timing[] = {
{ I960BASE_INSN_NOR1, model_i960KA_nor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR2, model_i960KA_nor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR3, model_i960KA_nor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR, model_i960KA_xnor, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR1, model_i960KA_xnor1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR2, model_i960KA_xnor2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR3, model_i960KA_xnor3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT, model_i960KA_not, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT1, model_i960KA_not1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT2, model_i960KA_not2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT3, model_i960KA_not3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT, model_i960KA_ornot, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT1, model_i960KA_ornot1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT2, model_i960KA_ornot2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT3, model_i960KA_ornot3, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT, model_i960KA_clrbit, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT1, model_i960KA_clrbit1, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT2, model_i960KA_clrbit2, { { (int) UNIT_I960KA_U_EXEC, 1, 1 } } },
@ -9456,10 +9720,18 @@ static const INSN_TIMING i960CA_timing[] = {
{ I960BASE_INSN_NOR1, model_i960CA_nor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR2, model_i960CA_nor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOR3, model_i960CA_nor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR, model_i960CA_xnor, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR1, model_i960CA_xnor1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR2, model_i960CA_xnor2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_XNOR3, model_i960CA_xnor3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT, model_i960CA_not, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT1, model_i960CA_not1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT2, model_i960CA_not2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_NOT3, model_i960CA_not3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT, model_i960CA_ornot, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT1, model_i960CA_ornot1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT2, model_i960CA_ornot2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_ORNOT3, model_i960CA_ornot3, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT, model_i960CA_clrbit, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT1, model_i960CA_clrbit1, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
{ I960BASE_INSN_CLRBIT2, model_i960CA_clrbit2, { { (int) UNIT_I960CA_U_EXEC, 1, 1 } } },
@ -9759,7 +10031,7 @@ i960_ka_sa_init_cpu (SIM_CPU *cpu)
const MACH i960_ka_sa_mach =
{
"i960:ka_sa", "i960:ka_sa",
"i960:ka_sa", "i960:ka_sa", MACH_I960_KA_SA,
32, 32, & i960_ka_sa_models[0], & i960base_imp_properties,
i960_ka_sa_init_cpu,
i960base_prepare_run
@ -9785,7 +10057,7 @@ i960_ca_init_cpu (SIM_CPU *cpu)
const MACH i960_ca_mach =
{
"i960:ca", "i960:ca",
"i960:ca", "i960:ca", MACH_I960_CA,
32, 32, & i960_ca_models[0], & i960base_imp_properties,
i960_ca_init_cpu,
i960base_prepare_run

678
sim/i960/sem-switch.c
View File

File diff suppressed because it is too large Load Diff

686
sim/i960/sem.c
View File

File diff suppressed because it is too large Load Diff

10
sim/i960/sim-if.c
View File

@ -31,7 +31,7 @@ static void free_state (SIM_DESC);
disassembler. */
static CGEN_DISASSEMBLER i960_disassemble_insn;
/* Records simulator descriptor so utilities like m32r_dump_regs can be
/* Records simulator descriptor so utilities like i960_dump_regs can be
called from gdb. */
SIM_DESC current_state;
@ -145,8 +145,8 @@ sim_open (kind, callback, abfd, argv)
/* Open a copy of the cpu descriptor table. */
{
CGEN_CPU_DESC cd = i960_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
CGEN_ENDIAN_LITTLE);
CGEN_CPU_DESC cd = i960_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
CGEN_ENDIAN_LITTLE);
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
@ -156,10 +156,10 @@ sim_open (kind, callback, abfd, argv)
}
/* Initialize various cgen things not done by common framework.
Must be done after m32r_cgen_cpu_open. */
Must be done after i960_cgen_cpu_open. */
cgen_init (sd);
/* Store in a global so things like sparc32_dump_regs can be invoked
/* Store in a global so things like i960_dump_regs can be invoked
from the gdb command line. */
current_state = sd;

42
sim/m32r/ChangeLog
View File

@ -1,3 +1,45 @@
Fri Apr 16 16:47:43 1999 Doug Evans <devans@charmed.cygnus.com>
* devices.c (device_io_read_buffer): New arg `sd'.
(device_io_write_buffer): New arg `sd'.
(device_error): Give proper arg spec.
1999-04-10 Doug Evans <devans@casey.cygnus.com>
* sem-switch.c,sem.c: Rebuild.
1999-03-27 Doug Evans <devans@casey.cygnus.com>
* decode.c: Rebuild.
1999-03-26 Doug Evans <devans@casey.cygnus.com>
* m32r-sim.h (M32R_DEVICE_LEN): Fix off by one error.
1999-03-22 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,model.c: Rebuild.
* m32r-sim.h (a_m32r_h_gr_get,a_m32r_h_gr_set): Declare.
(a_m32r_h_cr_get,a_m32r_h_cr_set): Declare.
* m32r.c (m32rbf_fetch_register): Replace calls to a_m32r_h_pc_get,
a_m32r_h_accum_get with appropriate calls to m32rbf_*.
(m32rbf_store_register): Ditto.
(a_m32r_h_gr_get,a_m32r_h_gr_set): New functions.
(a_m32r_h_cr_get,a_m32r_h_cr_set): Ditto.
* sim-if.c (sim_open): Update call to m32r_cgen_cpu_open.
* traps.c (m32r_core_signal): Replace calls to a_m32r_h_*,
with appropriate calls to m32rbf_*.
1999-03-11 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,cpu.c,cpu.h,sem.c,sem-switch.c: Rebuild.
* m32r-sim.h (GET_H_*,SET_H_*, except GET_H_SM): Delete.
* sim-if.c (sim_open): Update call to m32r_cgen_cpu_open.
1999-02-25 Doug Evans <devans@casey.cygnus.com>
* cpu.c,cpu.h: Rebuild.
1999-02-09 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (SIM_EXTRA_DEPS): Add m32r-desc.h, delete cpu-opc.h.

321
sim/m32r/arch.c
View File

@ -33,324 +33,3 @@ const MACH *sim_machs[] =
0
};
/* Get the value of h-pc. */
USI
a_m32r_h_pc_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_pc_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-pc. */
void
a_m32r_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_pc_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-gr. */
SI
a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
/* Set a value for h-gr. */
void
a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-cr. */
USI
a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_cr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
/* Set a value for h-cr. */
void
a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_cr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-accum. */
DI
a_m32r_h_accum_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_accum_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-accum. */
void
a_m32r_h_accum_set (SIM_CPU *current_cpu, DI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_accum_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-accums. */
DI
a_m32r_h_accums_get (SIM_CPU *current_cpu, UINT regno)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
default :
abort ();
}
}
/* Set a value for h-accums. */
void
a_m32r_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
default :
abort ();
}
}
/* Get the value of h-cond. */
BI
a_m32r_h_cond_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_cond_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-cond. */
void
a_m32r_h_cond_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_cond_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-psw. */
UQI
a_m32r_h_psw_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_psw_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-psw. */
void
a_m32r_h_psw_set (SIM_CPU *current_cpu, UQI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_psw_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-bpsw. */
UQI
a_m32r_h_bpsw_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_bpsw_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-bpsw. */
void
a_m32r_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_bpsw_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-bbpsw. */
UQI
a_m32r_h_bbpsw_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_bbpsw_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-bbpsw. */
void
a_m32r_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_bbpsw_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
/* Get the value of h-lock. */
BI
a_m32r_h_lock_get (SIM_CPU *current_cpu)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
return m32rbf_h_lock_get (current_cpu);
#endif
default :
abort ();
}
}
/* Set a value for h-lock. */
void
a_m32r_h_lock_set (SIM_CPU *current_cpu, BI newval)
{
switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
{
#ifdef HAVE_CPU_M32RBF
case bfd_mach_m32r :
m32rbf_h_lock_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}

22
sim/m32r/arch.h
View File

@ -27,28 +27,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define TARGET_BIG_ENDIAN 1
/* Cover fns for register access. */
USI a_m32r_h_pc_get (SIM_CPU *);
void a_m32r_h_pc_set (SIM_CPU *, USI);
SI a_m32r_h_gr_get (SIM_CPU *, UINT);
void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
USI a_m32r_h_cr_get (SIM_CPU *, UINT);
void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
DI a_m32r_h_accum_get (SIM_CPU *);
void a_m32r_h_accum_set (SIM_CPU *, DI);
DI a_m32r_h_accums_get (SIM_CPU *, UINT);
void a_m32r_h_accums_set (SIM_CPU *, UINT, DI);
BI a_m32r_h_cond_get (SIM_CPU *);
void a_m32r_h_cond_set (SIM_CPU *, BI);
UQI a_m32r_h_psw_get (SIM_CPU *);
void a_m32r_h_psw_set (SIM_CPU *, UQI);
UQI a_m32r_h_bpsw_get (SIM_CPU *);
void a_m32r_h_bpsw_set (SIM_CPU *, UQI);
UQI a_m32r_h_bbpsw_get (SIM_CPU *);
void a_m32r_h_bbpsw_set (SIM_CPU *, UQI);
BI a_m32r_h_lock_get (SIM_CPU *);
void a_m32r_h_lock_set (SIM_CPU *, BI);
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_M32R_D, MODEL_TEST

17
sim/m32r/cpu.c
View File

@ -26,6 +26,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define WANT_CPU_M32RBF
#include "sim-main.h"
#include "cgen-ops.h"
/* Get the value of h-pc. */
@ -91,22 +92,6 @@ m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
SET_H_ACCUM (newval);
}
/* Get the value of h-accums. */
DI
m32rbf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_ACCUMS (regno);
}
/* Set a value for h-accums. */
void
m32rbf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_ACCUMS (regno, newval);
}
/* Get the value of h-cond. */
BI

23
sim/m32r/cpu.h
View File

@ -46,20 +46,29 @@ typedef struct {
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/* control registers */
USI h_cr[16];
/* GET_H_CR macro user-written */
/* SET_H_CR macro user-written */
#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
#define SET_H_CR(index, x) \
do { \
m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
} while (0)
/* accumulator */
DI h_accum;
/* GET_H_ACCUM macro user-written */
/* SET_H_ACCUM macro user-written */
#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
#define SET_H_ACCUM(x) \
do { \
m32rbf_h_accum_set_handler (current_cpu, (x));\
} while (0)
/* condition bit */
BI h_cond;
#define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x))
/* psw part of psw */
UQI h_psw;
/* GET_H_PSW macro user-written */
/* SET_H_PSW macro user-written */
#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
#define SET_H_PSW(x) \
do { \
m32rbf_h_psw_set_handler (current_cpu, (x));\
} while (0)
/* backup psw */
UQI h_bpsw;
#define GET_H_BPSW() CPU (h_bpsw)
@ -85,8 +94,6 @@ USI m32rbf_h_cr_get (SIM_CPU *, UINT);
void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
DI m32rbf_h_accum_get (SIM_CPU *);
void m32rbf_h_accum_set (SIM_CPU *, DI);
DI m32rbf_h_accums_get (SIM_CPU *, UINT);
void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
BI m32rbf_h_cond_get (SIM_CPU *);
void m32rbf_h_cond_set (SIM_CPU *, BI);
UQI m32rbf_h_psw_get (SIM_CPU *);

918
sim/m32r/decode.c
View File

File diff suppressed because it is too large Load Diff

13
sim/m32r/devices.c
View File

@ -32,10 +32,8 @@ device m32r_devices;
int
device_io_read_buffer (device *me, void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_CPU *cpu, sim_cia cia)
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
SIM_DESC sd = CPU_STATE (cpu);
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
return nr_bytes;
@ -70,10 +68,8 @@ device_io_read_buffer (device *me, void *source, int space,
int
device_io_write_buffer (device *me, const void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_CPU *cpu, sim_cia cia)
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
SIM_DESC sd = CPU_STATE (cpu);
#if WITH_SCACHE
/* MSPR support is deprecated but is kept in for upward compatibility
with existing overlay support. */
@ -105,4 +101,7 @@ device_io_write_buffer (device *me, const void *source, int space,
return nr_bytes;
}
void device_error () {}
void
device_error (device *me, char *message, ...)
{
}

19
sim/m32r/m32r-sim.h
View File

@ -41,26 +41,19 @@ extern int m32r_decode_gdb_ctrl_regnum (int);
FIXME: Eventually move to cgen. */
#define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
extern SI a_m32r_h_gr_get (SIM_CPU *, UINT);
extern void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
extern USI a_m32r_h_cr_get (SIM_CPU *, UINT);
extern void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
#define GET_H_CR(regno) \
XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
#define SET_H_CR(regno, val) \
XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
extern UQI m32rbf_h_psw_get_handler (SIM_CPU *);
extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
#define GET_H_PSW() \
XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
#define SET_H_PSW(val) \
XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
extern DI m32rbf_h_accum_get_handler (SIM_CPU *);
extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
#define GET_H_ACCUM() \
XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
#define SET_H_ACCUM(val) \
XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
/* Misc. profile data. */
@ -189,7 +182,7 @@ do { \
/* Start address and length of all device support. */
#define M32R_DEVICE_ADDR 0xff000000
#define M32R_DEVICE_LEN 0x00ffffff
#define M32R_DEVICE_LEN 0x01000000
/* sim_core_attach device argument. */
extern device m32r_devices;

124
sim/m32r/m32r.c
View File

@ -48,6 +48,8 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
int
m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
int mach = MACH_NUM (CPU_MACH (current_cpu));
if (rn < 16)
SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
else
@ -64,13 +66,22 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
m32r_decode_gdb_ctrl_regnum (rn)));
break;
case PC_REGNUM :
SETTWI (buf, a_m32r_h_pc_get (current_cpu));
if (mach == MACH_M32R)
SETTWI (buf, m32rbf_h_pc_get (current_cpu));
else
SETTWI (buf, m32rxf_h_pc_get (current_cpu));
break;
case ACCL_REGNUM :
SETTWI (buf, GETLODI (a_m32r_h_accum_get (current_cpu)));
if (mach == MACH_M32R)
SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
break;
case ACCH_REGNUM :
SETTWI (buf, GETHIDI (a_m32r_h_accum_get (current_cpu)));
if (mach == MACH_M32R)
SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
else
SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
break;
default :
return 0;
@ -84,6 +95,8 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
int
m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
{
int mach = MACH_NUM (CPU_MACH (current_cpu));
if (rn < 16)
a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
else
@ -101,20 +114,37 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
GETTWI (buf));
break;
case PC_REGNUM :
a_m32r_h_pc_set (current_cpu, GETTWI (buf));
if (mach == MACH_M32R)
m32rbf_h_pc_set (current_cpu, GETTWI (buf));
else
m32rxf_h_pc_set (current_cpu, GETTWI (buf));
break;
case ACCL_REGNUM :
{
DI val = a_m32r_h_accum_get (current_cpu);
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
val = m32rxf_h_accum_get (current_cpu);
SETLODI (val, GETTWI (buf));
a_m32r_h_accum_set (current_cpu, val);
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
m32rxf_h_accum_set (current_cpu, val);
break;
}
case ACCH_REGNUM :
{
DI val = a_m32r_h_accum_get (current_cpu);
DI val;
if (mach == MACH_M32R)
val = m32rbf_h_accum_get (current_cpu);
else
val = m32rxf_h_accum_get (current_cpu);
SETHIDI (val, GETTWI (buf));
a_m32r_h_accum_set (current_cpu, val);
if (mach == MACH_M32R)
m32rbf_h_accum_set (current_cpu, val);
else
m32rxf_h_accum_set (current_cpu, val);
break;
}
default :
@ -124,6 +154,84 @@ m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len
return -1; /*FIXME*/
}
/* Cover fns for mach independent register accesses. */
SI
a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
return m32rbf_h_gr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
m32rbf_h_gr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
m32rxf_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
USI
a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
return m32rbf_h_cr_get (current_cpu, regno);
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
return m32rxf_h_cr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_M32RBF
case MACH_M32R :
m32rbf_h_cr_set (current_cpu, regno, newval);
break;
#endif
#ifdef HAVE_CPU_M32RXF
case MACH_M32RX :
m32rxf_h_cr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
USI
m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
{

2
sim/m32r/model.c
View File

@ -4160,7 +4160,7 @@ m32r_init_cpu (SIM_CPU *cpu)
const MACH m32r_mach =
{
"m32r", "m32r",
"m32r", "m32r", MACH_M32R,
32, 32, & m32r_models[0], & m32rbf_imp_properties,
m32r_init_cpu,
m32rbf_prepare_run

96
sim/m32r/sem-switch.c
View File

@ -508,8 +508,8 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
@ -522,7 +522,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -537,8 +537,8 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
{
@ -551,7 +551,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -566,8 +566,8 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
@ -580,7 +580,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -821,7 +821,7 @@ if (NESI (* FLD (i_src2), 0)) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
CPU (h_gr[((UINT) 14)]) = opval;
@ -832,7 +832,7 @@ do {
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
@ -849,7 +849,7 @@ do {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
do {
{
{
SI opval = ADDSI (pc, 4);
CPU (h_gr[((UINT) 14)]) = opval;
@ -860,7 +860,7 @@ do {
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
@ -1162,8 +1162,8 @@ if (NESI (* FLD (i_sr), 0)) {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
USI temp1;SI temp0;
{
SI temp0;USI temp1;
temp0 = ADDSI (ANDSI (pc, -4), 4);
temp1 = ANDSI (* FLD (i_sr), -4);
{
@ -1176,7 +1176,7 @@ do {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
@ -1403,8 +1403,8 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
SI temp1;SI temp0;
{
SI temp0;SI temp1;
temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4);
{
@ -1417,7 +1417,7 @@ do {
* FLD (i_sr) = opval;
TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -1489,18 +1489,18 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
BI opval = 1;
CPU (h_lock) = opval;
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -1891,7 +1891,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
DI tmp_tmp1;
tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
@ -1900,7 +1900,7 @@ do {
SET_H_ACCUM (opval);
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
}
} while (0);
}
#undef FLD
}
@ -1915,7 +1915,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
DI tmp_tmp1;
tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
@ -1933,7 +1933,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
SET_H_ACCUM (opval);
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
}
} while (0);
}
#undef FLD
}
@ -1949,7 +1949,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
@ -1963,14 +1963,14 @@ do {
{
UQI opval = CPU (h_bpsw);
SET_H_PSW (opval);
TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
UQI opval = CPU (h_bbpsw);
CPU (h_bpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
@ -2290,7 +2290,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
SI tmp_new_src2;
tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
{
@ -2303,7 +2303,7 @@ do {
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -2318,7 +2318,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
SI tmp_new_src2;
tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
{
@ -2331,7 +2331,7 @@ do {
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -2365,8 +2365,8 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
@ -2379,7 +2379,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -2394,8 +2394,8 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
@ -2408,7 +2408,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
#undef FLD
}
@ -2424,7 +2424,7 @@ do {
SEM_BRANCH_INIT
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
USI opval = GET_H_CR (((UINT) 6));
SET_H_CR (((UINT) 14), opval);
@ -2438,24 +2438,24 @@ do {
{
UQI opval = CPU (h_bpsw);
CPU (h_bbpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
}
{
UQI opval = GET_H_PSW ();
CPU (h_bpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
{
UQI opval = ANDQI (GET_H_PSW (), 128);
SET_H_PSW (opval);
TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
#undef FLD
@ -2471,7 +2471,7 @@ do {
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
if (CPU (h_lock)) {
{
SI opval = * FLD (i_src1);
@ -2483,9 +2483,9 @@ if (CPU (h_lock)) {
{
BI opval = 0;
CPU (h_lock) = opval;
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
} while (0);
}
abuf->written = written;
#undef FLD

96
sim/m32r/sem.c
View File

@ -380,8 +380,8 @@ SEM_FN_NAME (m32rbf,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = ADDSI (* FLD (i_dr), * FLD (i_sr));
temp1 = ADDOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
@ -394,7 +394,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -411,8 +411,8 @@ SEM_FN_NAME (m32rbf,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = ADDSI (* FLD (i_sr), FLD (f_simm16));
temp1 = ADDOFSI (* FLD (i_sr), FLD (f_simm16), 0);
{
@ -425,7 +425,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -442,8 +442,8 @@ SEM_FN_NAME (m32rbf,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = ADDCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = ADDCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
@ -456,7 +456,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -717,7 +717,7 @@ SEM_FN_NAME (m32rbf,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
SI opval = ADDSI (ANDSI (pc, -4), 4);
CPU (h_gr[((UINT) 14)]) = opval;
@ -728,7 +728,7 @@ do {
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
return vpc;
@ -747,7 +747,7 @@ SEM_FN_NAME (m32rbf,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
do {
{
{
SI opval = ADDSI (pc, 4);
CPU (h_gr[((UINT) 14)]) = opval;
@ -758,7 +758,7 @@ do {
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc, SEM_BRANCH_ADDR_CACHE (sem_arg));
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
return vpc;
@ -1088,8 +1088,8 @@ SEM_FN_NAME (m32rbf,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
USI temp1;SI temp0;
{
SI temp0;USI temp1;
temp0 = ADDSI (ANDSI (pc, -4), 4);
temp1 = ANDSI (* FLD (i_sr), -4);
{
@ -1102,7 +1102,7 @@ do {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
return vpc;
@ -1353,8 +1353,8 @@ SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
SI temp1;SI temp0;
{
SI temp0;SI temp1;
temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4);
{
@ -1367,7 +1367,7 @@ do {
* FLD (i_sr) = opval;
TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -1447,18 +1447,18 @@ SEM_FN_NAME (m32rbf,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
BI opval = 1;
CPU (h_lock) = opval;
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
{
SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -1891,7 +1891,7 @@ SEM_FN_NAME (m32rbf,rac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
DI tmp_tmp1;
tmp_tmp1 = SLLDI (GET_H_ACCUM (), 1);
tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
@ -1900,7 +1900,7 @@ do {
SET_H_ACCUM (opval);
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -1917,7 +1917,7 @@ SEM_FN_NAME (m32rbf,rach) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
DI tmp_tmp1;
tmp_tmp1 = ANDDI (GET_H_ACCUM (), MAKEDI (16777215, 0xffffffff));
if (ANDIF (GEDI (tmp_tmp1, MAKEDI (16383, 0x80000000)), LEDI (tmp_tmp1, MAKEDI (8388607, 0xffffffff)))) {
@ -1935,7 +1935,7 @@ if (ANDIF (GEDI (tmp_tmp1, MAKEDI (8388608, 0)), LEDI (tmp_tmp1, MAKEDI (1676083
SET_H_ACCUM (opval);
TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -1953,7 +1953,7 @@ SEM_FN_NAME (m32rbf,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
@ -1967,14 +1967,14 @@ do {
{
UQI opval = CPU (h_bpsw);
SET_H_PSW (opval);
TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
UQI opval = CPU (h_bbpsw);
CPU (h_bpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
return vpc;
@ -2328,7 +2328,7 @@ SEM_FN_NAME (m32rbf,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
SI tmp_new_src2;
tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
{
@ -2341,7 +2341,7 @@ do {
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -2358,7 +2358,7 @@ SEM_FN_NAME (m32rbf,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
SI tmp_new_src2;
tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
{
@ -2371,7 +2371,7 @@ do {
* FLD (i_src2) = opval;
TRACE_RESULT (current_cpu, abuf, "src2", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -2409,8 +2409,8 @@ SEM_FN_NAME (m32rbf,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = SUBSI (* FLD (i_dr), * FLD (i_sr));
temp1 = SUBOFSI (* FLD (i_dr), * FLD (i_sr), 0);
{
@ -2423,7 +2423,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -2440,8 +2440,8 @@ SEM_FN_NAME (m32rbf,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
BI temp1;SI temp0;
{
SI temp0;BI temp1;
temp0 = SUBCSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
temp1 = SUBCFSI (* FLD (i_dr), * FLD (i_sr), CPU (h_cond));
{
@ -2454,7 +2454,7 @@ do {
CPU (h_cond) = opval;
TRACE_RESULT (current_cpu, abuf, "condbit", 'x', opval);
}
} while (0);
}
return vpc;
#undef FLD
@ -2472,7 +2472,7 @@ SEM_FN_NAME (m32rbf,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
{
USI opval = GET_H_CR (((UINT) 6));
SET_H_CR (((UINT) 14), opval);
@ -2486,24 +2486,24 @@ do {
{
UQI opval = CPU (h_bpsw);
CPU (h_bbpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "bbpsw", 'x', opval);
}
{
UQI opval = GET_H_PSW ();
CPU (h_bpsw) = opval;
TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "bpsw", 'x', opval);
}
{
UQI opval = ANDQI (GET_H_PSW (), 128);
SET_H_PSW (opval);
TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "psw", 'x', opval);
}
{
SI opval = m32r_trap (current_cpu, pc, FLD (f_uimm4));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
} while (0);
}
SEM_BRANCH_FINI (vpc);
return vpc;
@ -2521,7 +2521,7 @@ SEM_FN_NAME (m32rbf,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
do {
{
if (CPU (h_lock)) {
{
SI opval = * FLD (i_src1);
@ -2533,9 +2533,9 @@ if (CPU (h_lock)) {
{
BI opval = 0;
CPU (h_lock) = opval;
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
TRACE_RESULT (current_cpu, abuf, "lock", 'x', opval);
}
} while (0);
}
abuf->written = written;
return vpc;

4
sim/m32r/sim-if.c
View File

@ -155,8 +155,8 @@ sim_open (kind, callback, abfd, argv)
/* Open a copy of the cpu descriptor table. */
{
CGEN_CPU_DESC cd = m32r_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
CGEN_ENDIAN_BIG);
CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
CGEN_ENDIAN_BIG);
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);

15
sim/m32r/traps.c
View File

@ -59,9 +59,18 @@ m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
{
a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
a_m32r_h_cr_get (current_cpu, H_CR_BPC));
a_m32r_h_bpsw_set (current_cpu, a_m32r_h_psw_get (current_cpu));
/* sm not changed */
a_m32r_h_psw_set (current_cpu, a_m32r_h_psw_get (current_cpu) & 0x80);
if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
{
m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
/* sm not changed */
m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
}
else
{
m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
/* sm not changed */
m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
}
a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,

21
sim/mips/ChangeLog
View File

@ -1,3 +1,24 @@
1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
* mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
* configure.in: Any mips64vr5*-*-* target should have
-DTARGET_ENABLE_FR=1.
(default_endian): Any mips64vr*el-*-* target should default to
LITTLE_ENDIAN.
* configure: Re-generate.
1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
* mips.igen (ldl): Extend from _16_, not 32.
Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
* interp.c (sim_store_register): Force registers written to by GDB
into an un-interpreted state.
1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
* dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the

241
sim/mips/configure vendored
View File

@ -135,7 +135,7 @@ sim_inline="-DDEFAULT_INLINE=0"
# Guess values for system-dependent variables and create Makefiles.
# Generated automatically using autoconf version 2.12.2
# Generated automatically using autoconf version 2.13
# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
#
# This configure script is free software; the Free Software Foundation
@ -511,7 +511,7 @@ EOF
verbose=yes ;;
-version | --version | --versio | --versi | --vers)
echo "configure generated by autoconf version 2.12.2"
echo "configure generated by autoconf version 2.13"
exit 0 ;;
-with-* | --with-*)
@ -1062,7 +1062,7 @@ else
#endif
EOF
if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
egrep "off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
rm -rf conftest*
ac_cv_type_off_t=yes
else
@ -1095,7 +1095,7 @@ else
#endif
EOF
if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
egrep "size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
rm -rf conftest*
ac_cv_type_size_t=yes
else
@ -1755,7 +1755,8 @@ else
ac_cv_prog_CC="$CC" # Let the user override the test.
else
IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
for ac_dir in $PATH; do
ac_dummy="$PATH"
for ac_dir in $ac_dummy; do
test -z "$ac_dir" && ac_dir=.
if test -f $ac_dir/$ac_word; then
ac_cv_prog_CC="gcc"
@ -1776,7 +1777,7 @@ if test -z "$CC"; then
# Extract the first word of "cc", so it can be a program name with args.
set dummy cc; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:1780: checking for $ac_word" >&5
echo "configure:1781: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -1785,7 +1786,8 @@ else
else
IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
ac_prog_rejected=no
for ac_dir in $PATH; do
ac_dummy="$PATH"
for ac_dir in $ac_dummy; do
test -z "$ac_dir" && ac_dir=.
if test -f $ac_dir/$ac_word; then
if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
@ -1826,7 +1828,7 @@ fi
# Extract the first word of "cl", so it can be a program name with args.
set dummy cl; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:1830: checking for $ac_word" >&5
echo "configure:1832: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -1834,7 +1836,8 @@ else
ac_cv_prog_CC="$CC" # Let the user override the test.
else
IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
for ac_dir in $PATH; do
ac_dummy="$PATH"
for ac_dir in $ac_dummy; do
test -z "$ac_dir" && ac_dir=.
if test -f $ac_dir/$ac_word; then
ac_cv_prog_CC="cl"
@ -1857,7 +1860,7 @@ fi
fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
echo "configure:1861: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
echo "configure:1864: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
ac_ext=c
# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
@ -1866,12 +1869,14 @@ ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
cross_compiling=$ac_cv_prog_cc_cross
cat > conftest.$ac_ext <<EOF
#line 1871 "configure"
cat > conftest.$ac_ext << EOF
#line 1875 "configure"
#include "confdefs.h"
main(){return(0);}
EOF
if { (eval echo configure:1875: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:1880: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
ac_cv_prog_cc_works=yes
# If we can't run a trivial program, we are probably using a cross compiler.
if (./conftest; exit) 2>/dev/null; then
@ -1885,18 +1890,24 @@ else
ac_cv_prog_cc_works=no
fi
rm -fr conftest*
ac_ext=c
# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
ac_cpp='$CPP $CPPFLAGS'
ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
cross_compiling=$ac_cv_prog_cc_cross
echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
if test $ac_cv_prog_cc_works = no; then
{ echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
fi
echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
echo "configure:1895: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
echo "configure:1906: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
cross_compiling=$ac_cv_prog_cc_cross
echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
echo "configure:1900: checking whether we are using GNU C" >&5
echo "configure:1911: checking whether we are using GNU C" >&5
if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -1905,7 +1916,7 @@ else
yes;
#endif
EOF
if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1909: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1920: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
ac_cv_prog_gcc=yes
else
ac_cv_prog_gcc=no
@ -1924,7 +1935,7 @@ ac_test_CFLAGS="${CFLAGS+set}"
ac_save_CFLAGS="$CFLAGS"
CFLAGS=
echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
echo "configure:1928: checking whether ${CC-cc} accepts -g" >&5
echo "configure:1939: checking whether ${CC-cc} accepts -g" >&5
if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -1967,7 +1978,7 @@ fi
# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
# ./install, which can be erroneously created by make from ./install.sh.
echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
echo "configure:1971: checking for a BSD compatible install" >&5
echo "configure:1982: checking for a BSD compatible install" >&5
if test -z "$INSTALL"; then
if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@ -2015,6 +2026,8 @@ echo "$ac_t""$INSTALL" 1>&6
# It thinks the first close brace ends the variable substitution.
test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
@ -2033,7 +2046,7 @@ AR=${AR-ar}
# Extract the first word of "ranlib", so it can be a program name with args.
set dummy ranlib; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:2037: checking for $ac_word" >&5
echo "configure:2050: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -2041,7 +2054,8 @@ else
ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
else
IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
for ac_dir in $PATH; do
ac_dummy="$PATH"
for ac_dir in $ac_dummy; do
test -z "$ac_dir" && ac_dir=.
if test -f $ac_dir/$ac_word; then
ac_cv_prog_RANLIB="ranlib"
@ -2067,17 +2081,17 @@ unistd.h values.h sys/param.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:2071: checking for $ac_hdr" >&5
echo "configure:2085: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2076 "configure"
#line 2090 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:2081: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:2095: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -2107,12 +2121,12 @@ done
__argz_count __argz_stringify __argz_next
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:2111: checking for $ac_func" >&5
echo "configure:2125: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2116 "configure"
#line 2130 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -2135,7 +2149,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:2139: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2153: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@ -2164,12 +2178,12 @@ done
for ac_func in stpcpy
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:2168: checking for $ac_func" >&5
echo "configure:2182: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2173 "configure"
#line 2187 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -2192,7 +2206,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:2196: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2210: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@ -2226,19 +2240,19 @@ EOF
if test $ac_cv_header_locale_h = yes; then
echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
echo "configure:2230: checking for LC_MESSAGES" >&5
echo "configure:2244: checking for LC_MESSAGES" >&5
if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2235 "configure"
#line 2249 "configure"
#include "confdefs.h"
#include <locale.h>
int main() {
return LC_MESSAGES
; return 0; }
EOF
if { (eval echo configure:2242: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2256: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
am_cv_val_LC_MESSAGES=yes
else
@ -2259,7 +2273,7 @@ EOF
fi
fi
echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
echo "configure:2263: checking whether NLS is requested" >&5
echo "configure:2277: checking whether NLS is requested" >&5
# Check whether --enable-nls or --disable-nls was given.
if test "${enable_nls+set}" = set; then
enableval="$enable_nls"
@ -2279,7 +2293,7 @@ fi
EOF
echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
echo "configure:2283: checking whether included gettext is requested" >&5
echo "configure:2297: checking whether included gettext is requested" >&5
# Check whether --with-included-gettext or --without-included-gettext was given.
if test "${with_included_gettext+set}" = set; then
withval="$with_included_gettext"
@ -2298,17 +2312,17 @@ fi
ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
echo "configure:2302: checking for libintl.h" >&5
echo "configure:2316: checking for libintl.h" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2307 "configure"
#line 2321 "configure"
#include "confdefs.h"
#include <libintl.h>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:2312: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:2326: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -2325,19 +2339,19 @@ fi
if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
echo "$ac_t""yes" 1>&6
echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
echo "configure:2329: checking for gettext in libc" >&5
echo "configure:2343: checking for gettext in libc" >&5
if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2334 "configure"
#line 2348 "configure"
#include "confdefs.h"
#include <libintl.h>
int main() {
return (int) gettext ("")
; return 0; }
EOF
if { (eval echo configure:2341: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2355: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
gt_cv_func_gettext_libc=yes
else
@ -2353,7 +2367,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
if test "$gt_cv_func_gettext_libc" != "yes"; then
echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
echo "configure:2357: checking for bindtextdomain in -lintl" >&5
echo "configure:2371: checking for bindtextdomain in -lintl" >&5
ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@ -2361,7 +2375,7 @@ else
ac_save_LIBS="$LIBS"
LIBS="-lintl $LIBS"
cat > conftest.$ac_ext <<EOF
#line 2365 "configure"
#line 2379 "configure"
#include "confdefs.h"
/* Override any gcc2 internal prototype to avoid an error. */
/* We use char because int might match the return type of a gcc2
@ -2372,7 +2386,7 @@ int main() {
bindtextdomain()
; return 0; }
EOF
if { (eval echo configure:2376: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2390: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_lib_$ac_lib_var=yes"
else
@ -2388,19 +2402,19 @@ fi
if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
echo "$ac_t""yes" 1>&6
echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
echo "configure:2392: checking for gettext in libintl" >&5
echo "configure:2406: checking for gettext in libintl" >&5
if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2397 "configure"
#line 2411 "configure"
#include "confdefs.h"
int main() {
return (int) gettext ("")
; return 0; }
EOF
if { (eval echo configure:2404: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2418: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
gt_cv_func_gettext_libintl=yes
else
@ -2428,7 +2442,7 @@ EOF
# Extract the first word of "msgfmt", so it can be a program name with args.
set dummy msgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:2432: checking for $ac_word" >&5
echo "configure:2446: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -2462,12 +2476,12 @@ fi
for ac_func in dcgettext
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:2466: checking for $ac_func" >&5
echo "configure:2480: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2471 "configure"
#line 2485 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -2490,7 +2504,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:2494: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2508: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@ -2517,7 +2531,7 @@ done
# Extract the first word of "gmsgfmt", so it can be a program name with args.
set dummy gmsgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:2521: checking for $ac_word" >&5
echo "configure:2535: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -2530,7 +2544,8 @@ else
;;
*)
IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
for ac_dir in $PATH; do
ac_dummy="$PATH"
for ac_dir in $ac_dummy; do
test -z "$ac_dir" && ac_dir=.
if test -f $ac_dir/$ac_word; then
ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
@ -2552,7 +2567,7 @@ fi
# Extract the first word of "xgettext", so it can be a program name with args.
set dummy xgettext; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:2556: checking for $ac_word" >&5
echo "configure:2571: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -2584,7 +2599,7 @@ else
fi
cat > conftest.$ac_ext <<EOF
#line 2588 "configure"
#line 2603 "configure"
#include "confdefs.h"
int main() {
@ -2592,7 +2607,7 @@ extern int _nl_msg_cat_cntr;
return _nl_msg_cat_cntr
; return 0; }
EOF
if { (eval echo configure:2596: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:2611: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
CATOBJEXT=.gmo
DATADIRNAME=share
@ -2624,7 +2639,7 @@ fi
# Extract the first word of "msgfmt", so it can be a program name with args.
set dummy msgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:2628: checking for $ac_word" >&5
echo "configure:2643: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -2658,7 +2673,7 @@ fi
# Extract the first word of "gmsgfmt", so it can be a program name with args.
set dummy gmsgfmt; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:2662: checking for $ac_word" >&5
echo "configure:2677: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -2671,7 +2686,8 @@ else
;;
*)
IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
for ac_dir in $PATH; do
ac_dummy="$PATH"
for ac_dir in $ac_dummy; do
test -z "$ac_dir" && ac_dir=.
if test -f $ac_dir/$ac_word; then
ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
@ -2693,7 +2709,7 @@ fi
# Extract the first word of "xgettext", so it can be a program name with args.
set dummy xgettext; ac_word=$2
echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
echo "configure:2697: checking for $ac_word" >&5
echo "configure:2713: checking for $ac_word" >&5
if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -2783,7 +2799,7 @@ fi
LINGUAS=
else
echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
echo "configure:2787: checking for catalogs to be installed" >&5
echo "configure:2803: checking for catalogs to be installed" >&5
NEW_LINGUAS=
for lang in ${LINGUAS=$ALL_LINGUAS}; do
case "$ALL_LINGUAS" in
@ -2811,17 +2827,17 @@ echo "configure:2787: checking for catalogs to be installed" >&5
if test "$CATOBJEXT" = ".cat"; then
ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
echo "configure:2815: checking for linux/version.h" >&5
echo "configure:2831: checking for linux/version.h" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2820 "configure"
#line 2836 "configure"
#include "confdefs.h"
#include <linux/version.h>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:2825: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:2841: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -2890,17 +2906,17 @@ for ac_hdr in stdlib.h string.h strings.h unistd.h time.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:2894: checking for $ac_hdr" >&5
echo "configure:2910: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2899 "configure"
#line 2915 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:2904: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:2920: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -2930,17 +2946,17 @@ for ac_hdr in sys/time.h sys/resource.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:2934: checking for $ac_hdr" >&5
echo "configure:2950: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2939 "configure"
#line 2955 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:2944: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:2960: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -2970,17 +2986,17 @@ for ac_hdr in fcntl.h fpu_control.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:2974: checking for $ac_hdr" >&5
echo "configure:2990: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 2979 "configure"
#line 2995 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:2984: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:3000: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -3010,17 +3026,17 @@ for ac_hdr in dlfcn.h errno.h sys/stat.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:3014: checking for $ac_hdr" >&5
echo "configure:3030: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 3019 "configure"
#line 3035 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:3024: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:3040: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -3049,12 +3065,12 @@ done
for ac_func in getrusage time sigaction __setfpucw
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:3053: checking for $ac_func" >&5
echo "configure:3069: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 3058 "configure"
#line 3074 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -3077,7 +3093,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:3081: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:3097: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@ -3104,7 +3120,7 @@ done
# Check for socket libraries
echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6
echo "configure:3108: checking for bind in -lsocket" >&5
echo "configure:3124: checking for bind in -lsocket" >&5
ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@ -3112,7 +3128,7 @@ else
ac_save_LIBS="$LIBS"
LIBS="-lsocket $LIBS"
cat > conftest.$ac_ext <<EOF
#line 3116 "configure"
#line 3132 "configure"
#include "confdefs.h"
/* Override any gcc2 internal prototype to avoid an error. */
/* We use char because int might match the return type of a gcc2
@ -3123,7 +3139,7 @@ int main() {
bind()
; return 0; }
EOF
if { (eval echo configure:3127: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:3143: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_lib_$ac_lib_var=yes"
else
@ -3151,7 +3167,7 @@ else
fi
echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6
echo "configure:3155: checking for gethostbyname in -lnsl" >&5
echo "configure:3171: checking for gethostbyname in -lnsl" >&5
ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@ -3159,7 +3175,7 @@ else
ac_save_LIBS="$LIBS"
LIBS="-lnsl $LIBS"
cat > conftest.$ac_ext <<EOF
#line 3163 "configure"
#line 3179 "configure"
#include "confdefs.h"
/* Override any gcc2 internal prototype to avoid an error. */
/* We use char because int might match the return type of a gcc2
@ -3170,7 +3186,7 @@ int main() {
gethostbyname()
; return 0; }
EOF
if { (eval echo configure:3174: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:3190: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_lib_$ac_lib_var=yes"
else
@ -3346,12 +3362,12 @@ fi
echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6
echo "configure:3350: checking return type of signal handlers" >&5
echo "configure:3366: checking return type of signal handlers" >&5
if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 3355 "configure"
#line 3371 "configure"
#include "confdefs.h"
#include <sys/types.h>
#include <signal.h>
@ -3368,7 +3384,7 @@ int main() {
int i;
; return 0; }
EOF
if { (eval echo configure:3372: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
if { (eval echo configure:3388: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_type_signal=void
else
@ -3388,7 +3404,7 @@ EOF
echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
echo "configure:3392: checking for executable suffix" >&5
echo "configure:3408: checking for executable suffix" >&5
if eval "test \"`echo '$''{'am_cv_exeext'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
@ -3541,14 +3557,14 @@ else
if test "x$cross_compiling" = "xno"; then
echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
echo "configure:3545: checking whether byte ordering is bigendian" >&5
echo "configure:3561: checking whether byte ordering is bigendian" >&5
if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
ac_cv_c_bigendian=unknown
# See if sys/param.h defines the BYTE_ORDER macro.
cat > conftest.$ac_ext <<EOF
#line 3552 "configure"
#line 3568 "configure"
#include "confdefs.h"
#include <sys/types.h>
#include <sys/param.h>
@ -3559,11 +3575,11 @@ int main() {
#endif
; return 0; }
EOF
if { (eval echo configure:3563: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
if { (eval echo configure:3579: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
# It does; now see whether it defined to BIG_ENDIAN or not.
cat > conftest.$ac_ext <<EOF
#line 3567 "configure"
#line 3583 "configure"
#include "confdefs.h"
#include <sys/types.h>
#include <sys/param.h>
@ -3574,7 +3590,7 @@ int main() {
#endif
; return 0; }
EOF
if { (eval echo configure:3578: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
if { (eval echo configure:3594: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
rm -rf conftest*
ac_cv_c_bigendian=yes
else
@ -3594,7 +3610,7 @@ if test "$cross_compiling" = yes; then
{ echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
else
cat > conftest.$ac_ext <<EOF
#line 3598 "configure"
#line 3614 "configure"
#include "confdefs.h"
main () {
/* Are we little or big endian? From Harbison&Steele. */
@ -3607,7 +3623,7 @@ main () {
exit (u.c[sizeof (long) - 1] == 1);
}
EOF
if { (eval echo configure:3611: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
if { (eval echo configure:3627: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
then
ac_cv_c_bigendian=no
else
@ -3683,6 +3699,7 @@ mips_endian=
default_endian=
case "${target}" in
mips64el*-*-*) mips_endian=LITTLE_ENDIAN ;;
mips64vr*el-*-*) default_endian=LITTLE_ENDIAN ;;
mips64*-*-*) default_endian=BIG_ENDIAN ;;
mips16*-*-*) default_endian=BIG_ENDIAN ;;
mips*-*-*) default_endian=BIG_ENDIAN ;;
@ -4021,7 +4038,7 @@ esac
# Uses ac_ vars as temps to allow command line to override cache and checks.
# --without-x overrides everything else, but does not touch the cache.
echo $ac_n "checking for X""... $ac_c" 1>&6
echo "configure:4125: checking for X" >&5
echo "configure:4142: checking for X" >&5
# Check whether --with-x or --without-x was given.
if test "${with_x+set}" = set; then
@ -4083,12 +4100,12 @@ if test "$ac_x_includes" = NO; then
# First, try using that file with no special directory specified.
cat > conftest.$ac_ext <<EOF
#line 4187 "configure"
#line 4204 "configure"
#include "confdefs.h"
#include <$x_direct_test_include>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:4192: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:4209: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -4157,14 +4174,14 @@ if test "$ac_x_libraries" = NO; then
ac_save_LIBS="$LIBS"
LIBS="-l$x_direct_test_library $LIBS"
cat > conftest.$ac_ext <<EOF
#line 4261 "configure"
#line 4278 "configure"
#include "confdefs.h"
int main() {
${x_direct_test_function}()
; return 0; }
EOF
if { (eval echo configure:4268: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:4285: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
LIBS="$ac_save_LIBS"
# We can link X programs with no special library path.
@ -4257,17 +4274,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h
do
ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
echo "configure:5155: checking for $ac_hdr" >&5
echo "configure:5172: checking for $ac_hdr" >&5
if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 5160 "configure"
#line 5177 "configure"
#include "confdefs.h"
#include <$ac_hdr>
EOF
ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
{ (eval echo configure:5165: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
{ (eval echo configure:5182: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
if test -z "$ac_err"; then
rm -rf conftest*
@ -4294,7 +4311,7 @@ fi
done
echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
echo "configure:5192: checking for fabs in -lm" >&5
echo "configure:5209: checking for fabs in -lm" >&5
ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
@ -4302,7 +4319,7 @@ else
ac_save_LIBS="$LIBS"
LIBS="-lm $LIBS"
cat > conftest.$ac_ext <<EOF
#line 5200 "configure"
#line 5217 "configure"
#include "confdefs.h"
/* Override any gcc2 internal prototype to avoid an error. */
/* We use char because int might match the return type of a gcc2
@ -4313,7 +4330,7 @@ int main() {
fabs()
; return 0; }
EOF
if { (eval echo configure:5211: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:5228: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_lib_$ac_lib_var=yes"
else
@ -4343,12 +4360,12 @@ fi
for ac_func in aint anint sqrt
do
echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
echo "configure:5241: checking for $ac_func" >&5
echo "configure:5258: checking for $ac_func" >&5
if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
else
cat > conftest.$ac_ext <<EOF
#line 5246 "configure"
#line 5263 "configure"
#include "confdefs.h"
/* System header to define __stub macros and hopefully few prototypes,
which can conflict with char $ac_func(); below. */
@ -4371,7 +4388,7 @@ $ac_func();
; return 0; }
EOF
if { (eval echo configure:5269: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
if { (eval echo configure:5286: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
rm -rf conftest*
eval "ac_cv_func_$ac_func=yes"
else
@ -4421,7 +4438,7 @@ EOF
# Ultrix sh set writes to stderr and can't be redirected directly,
# and sets the high bit in the cache file unless we assign to the vars.
(set) 2>&1 |
case `(ac_space=' '; set) 2>&1 | grep ac_space` in
case `(ac_space=' '; set | grep ac_space) 2>&1` in
*ac_space=\ *)
# `set' does not quote correctly, so add quotes (double-quote substitution
# turns \\\\ into \\, and sed turns \\ into \).
@ -4488,7 +4505,7 @@ do
echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
-version | --version | --versio | --versi | --vers | --ver | --ve | --v)
echo "$CONFIG_STATUS generated by autoconf version 2.12.2"
echo "$CONFIG_STATUS generated by autoconf version 2.13"
exit 0 ;;
-help | --help | --hel | --he | --h)
echo "\$ac_cs_usage"; exit 0 ;;
@ -4532,6 +4549,7 @@ s%@SHELL@%$SHELL%g
s%@CFLAGS@%$CFLAGS%g
s%@CPPFLAGS@%$CPPFLAGS%g
s%@CXXFLAGS@%$CXXFLAGS%g
s%@FFLAGS@%$FFLAGS%g
s%@DEFS@%$DEFS%g
s%@LDFLAGS@%$LDFLAGS%g
s%@LIBS@%$LIBS%g
@ -4567,6 +4585,7 @@ s%@build_vendor@%$build_vendor%g
s%@build_os@%$build_os%g
s%@CC@%$CC%g
s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g
s%@INSTALL_DATA@%$INSTALL_DATA%g
s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g
s%@HDEFINES@%$HDEFINES%g

1
sim/mips/configure.in
View File

@ -32,6 +32,7 @@ mips_endian=
default_endian=
case "${target}" in
mips64el*-*-*) mips_endian=LITTLE_ENDIAN ;;
mips64vr*el-*-*) default_endian=LITTLE_ENDIAN ;;
mips64*-*-*) default_endian=BIG_ENDIAN ;;
mips16*-*-*) default_endian=BIG_ENDIAN ;;
mips*-*-*) default_endian=BIG_ENDIAN ;;

1
sim/mips/interp.c
View File

@ -750,6 +750,7 @@ sim_store_register (sd,rn,memory,length)
if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
{
cpu->fpr_state[rn - FGRIDX] = fmt_uninterpreted;
if (cpu->register_widths[rn] == 32)
{
cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);

10
sim/mips/mips.igen
View File

@ -1551,7 +1551,7 @@
*vr5000:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
}
@ -3738,6 +3738,14 @@
*vr4100:
*vr5000:
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
// stub needed for eCos as tx39 hardware bug workaround
*r3900:
{
/* do nothing */
}
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
"bc0fl <OFFSET>"

15
sim/mn10200/ChangeLog
View File

@ -1,3 +1,18 @@
1999-04-06 Keith Seitz <keiths@cygnus.com>
* interp.c (sim_stop): Set the sim's exception
to SIGINT.
1999-04-02 Keith Seitz <keiths@cygnus.com>
* interp.c (UI_LOOP_POLL_INTERVAL): Define. Used to tweak the
frequency at which ui_loop_hook is called.
(ui_loop_hook_counter): New global defined when NEED_UI_LOOP_HOOK
is defined.
(sim_resume): Call ui_loop_hook (if defined) when the interval
passes.
* Makefile.in (SIM_EXTRA_CFLAGS): Include NEED_UI_LOOP_HOOK.
Wed Jun 17 11:37:59 1998 Mark Alexander <marka@cygnus.com>
* Makefile.in: Define NL_TARGET so that targ-vals.h will be used

2
sim/mn10200/Makefile.in
View File

@ -19,7 +19,7 @@
## COMMON_PRE_CONFIG_FRAG
SIM_OBJS = interp.o table.o simops.o sim-load.o
SIM_EXTRA_CFLAGS = -I$(srcdir)/../../newlib/libc/sys/sysmec
SIM_EXTRA_CFLAGS = -I$(srcdir)/../../newlib/libc/sys/sysmec -DNEED_UI_LOOP_HOOK
SIM_EXTRA_CLEAN = clean-extra
# Select mn10200 support in nltvals.def.

22
sim/mn10200/interp.c
View File

@ -4,6 +4,17 @@
#include "mn10200_sim.h"
#ifdef NEED_UI_LOOP_HOOK
/* How often to run the ui_loop update, when in use */
#define UI_LOOP_POLL_INTERVAL 0x60000
/* Counter for the ui_loop_hook update */
static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
/* Actual hook to call to run through gdb's gui event loop */
extern int (*ui_loop_hook) (int);
#endif /* NEED_UI_LOOP_HOOK */
host_callback *mn10200_callback;
int mn10200_debug;
static SIM_OPEN_KIND sim_kind;
@ -292,7 +303,8 @@ int
sim_stop (sd)
SIM_DESC sd;
{
return 0;
State.exception = SIGINT;
return 1;
}
void
@ -313,6 +325,14 @@ sim_resume (sd, step, siggnal)
{
unsigned long insn, extension;
#ifdef NEED_UI_LOOP_HOOK
if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
{
ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
ui_loop_hook (0);
}
#endif /* NEED_UI_LOOP_HOOK */
/* Fetch the current instruction, fetch a double word to
avoid redundant fetching for the common cases below. */
inst = load_mem_big (PC, 2);

25
sim/mn10300/ChangeLog
View File

@ -1,3 +1,28 @@
1999-04-16 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (program_interrupt): Detect undesired recursion using
static flag. Set NMIRC register's SYSEF flag during
--board=stdeval1 mode.
* dv-mn103-int.c (write_icr): Add backdoor address to allow CPU to
set SYSEF flag.
1999-04-02 Keith Seitz <keiths@cygnus.com>
* Makefile.in (SIM_EXTRA_CFLAGS): Define a POLL_QUIT_INTERVAL
for use in the simulator so that the poll_quit callback is
not called too often.
Tue Mar 9 21:26:41 1999 Andrew Cagney <cagney@b1.cygnus.com>
* dv-mn103int.c (mn103int_ioctl): Return something.
* dv-mn103tim.c (write_tm6md): GCC suggested parentheses around &&
within ||.
Tue Feb 16 23:57:17 1999 Jeffrey A Law (law@cygnus.com)
* mn10300.igen (retf): Fix return address computation and store
the new pc value into nia.
1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
* Makefile.in (WITH_COMMON_OBJS): Build also dv-sockser.o.

2
sim/mn10300/Makefile.in
View File

@ -51,7 +51,7 @@ NL_TARGET = -DNL_TARGET_mn10300
INCLUDE = mn10300_sim.h $(srcdir)/../../include/callback.h
# List of extra flags to always pass to $(CC).
SIM_EXTRA_CFLAGS = @sim_gen@
SIM_EXTRA_CFLAGS = @sim_gen@ -DPOLL_QUIT_INTERVAL=0x20
## COMMON_POST_CONFIG_FRAG

7
sim/mn10300/dv-mn103int.c
View File

@ -585,6 +585,12 @@ write_icr (struct hw *me,
group->gid, val));
group->request &= ~EXTRACT_ID (val);
break;
/* Special backdoor access to SYSEF flag from CPU. See
interp.c:program_interrupt(). */
case 3:
HW_TRACE ((me, "write-icr-special group=%d:0 nmi 0x%02x",
group->gid, val));
group->request |= EXTRACT_ID (val);
default:
break;
}
@ -815,6 +821,7 @@ mn103int_ioctl(struct hw *me,
struct mn103int *controller = (struct mn103int *)hw_data(me);
controller->group[0].request = EXTRACT_ID(4);
mn103int_port_event(me, 2 /* nmi_port(syserr) */, NULL, 0, 0);
return 0;
}

2
sim/mn10300/dv-mn103tim.c
View File

@ -842,7 +842,7 @@ write_tm6md (struct hw *me,
unsigned_word offset = address - timers->block[0].base;
if ( offset != 0x84 && nr_bytes > 1 || nr_bytes > 2 )
if ((offset != 0x84 && nr_bytes > 1) || nr_bytes > 2 )
{
hw_abort (me, "Bad write size of %d bytes to TM6MD", nr_bytes);
}

28
sim/mn10300/interp.c
View File

@ -1329,19 +1329,39 @@ program_interrupt (SIM_DESC sd,
{
int status;
struct hw *device;
static int in_interrupt = 0;
#ifdef SIM_CPU_EXCEPTION_TRIGGER
SIM_CPU_EXCEPTION_TRIGGER(sd,cpu,cia);
#endif
/* copy NMI handler code from dv-mn103cpu.c */
/* XXX: possible infinite recursion if these store_*() calls fail! */
store_word (SP - 4, CIA_GET (cpu));
store_half (SP - 8, PSW);
/* avoid infinite recursion */
if (in_interrupt)
{
(*mn10300_callback->printf_filtered) (mn10300_callback,
"ERROR: recursion in program_interrupt during software exception dispatch.");
}
else
{
in_interrupt = 1;
/* copy NMI handler code from dv-mn103cpu.c */
store_word (SP - 4, CIA_GET (cpu));
store_half (SP - 8, PSW);
/* Set the SYSEF flag in NMICR by backdoor method. See
dv-mn103int.c:write_icr(). This is necessary because
software exceptions are not modelled by actually talking to
the interrupt controller, so it cannot set its own SYSEF
flag. */
if ((NULL != board) && (strcmp(board, BOARD_AM32) == 0))
store_byte (0x34000103, 0x04);
}
PSW &= ~PSW_IE;
SP = SP - 8;
CIA_SET (cpu, 0x40000008);
in_interrupt = 0;
sim_engine_halt(sd, cpu, NULL, cia, sim_stopped, sig);
}

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