qemu/MAINTAINERS

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QEMU Maintainers
================
The intention of this file is not to establish who owns what portions of the
code base, but to provide a set of names that developers can consult when they
have a question about a particular subset and also to provide a set of names
to be CC'd when submitting a patch to obtain appropriate review.
In general, if you have a question about inclusion of a patch, you should
consult qemu-devel and not any specific individual privately.
Descriptions of section entries:
M: Mail patches to: FullName <address@domain>
Maintainers are looking after a certain area and must be CCed on
patches. They are considered the main contact point.
R: Designated reviewer: FullName <address@domain>
These reviewers should be CCed on patches.
Reviewers are familiar with the subject matter and provide feedback
even though they are not maintainers.
L: Mailing list that is relevant to this area
These lists should be CCed on patches.
W: Web-page with status/info
Q: Patchwork web based patch tracking system site
T: SCM tree type and location. Type is one of: git, hg, quilt, stgit.
S: Status, one of the following (keep in sync with docs/devel/maintainers.rst):
Supported: Someone is actually paid to look after this.
Maintained: Someone actually looks after it.
Odd Fixes: It has a maintainer but they don't have time to do
much other than throw the odd patch in. See below.
Orphan: No current maintainer [but maybe you could take the
role as you write your new code].
Obsolete: Old code. Something tagged obsolete generally means
it has been replaced by a better system and you
should be using that.
F: Files and directories with wildcard patterns.
A trailing slash includes all files and subdirectory files.
F: drivers/net/ all files in and below drivers/net
F: drivers/net/* all files in drivers/net, but not below
F: */net/* all files in "any top level directory"/net
One pattern per line. Multiple F: lines acceptable.
X: Files and directories that are NOT maintained, same rules as F:
Files exclusions are tested before file matches.
Can be useful for excluding a specific subdirectory, for instance:
F: net/
X: net/ipv6/
matches all files in and below net excluding net/ipv6/
K: Keyword perl extended regex pattern to match content in a
patch or file. For instance:
K: of_get_profile
matches patches or files that contain "of_get_profile"
K: \b(printk|pr_(info|err))\b
matches patches or files that contain one or more of the words
printk, pr_info or pr_err
One regex pattern per line. Multiple K: lines acceptable.
General Project Administration
------------------------------
M: Peter Maydell <peter.maydell@linaro.org>
All patches CC here
L: qemu-devel@nongnu.org
F: *
F: */
Project policy and developer guides
R: Alex Bennée <alex.bennee@linaro.org>
R: Daniel P. Berrangé <berrange@redhat.com>
R: Thomas Huth <thuth@redhat.com>
R: Markus Armbruster <armbru@redhat.com>
R: Philippe Mathieu-Daudé <philmd@linaro.org>
W: https://www.qemu.org/docs/master/devel/index.html
S: Odd Fixes
F: docs/devel/style.rst
F: docs/devel/code-of-conduct.rst
F: docs/devel/conflict-resolution.rst
F: docs/devel/submitting-a-patch.rst
F: docs/devel/submitting-a-pull-request.rst
Responsible Disclosure, Reporting Security Issues
-------------------------------------------------
W: https://wiki.qemu.org/SecurityProcess
M: Michael S. Tsirkin <mst@redhat.com>
L: secalert@redhat.com
Trivial patches
---------------
Trivial patches
M: Michael Tokarev <mjt@tls.msk.ru>
M: Laurent Vivier <laurent@vivier.eu>
S: Maintained
L: qemu-trivial@nongnu.org
K: ^Subject:.*(?i)trivial
F: docs/devel/trivial-patches.rst
T: git git://git.corpit.ru/qemu.git trivial-patches
T: git https://github.com/vivier/qemu.git trivial-patches
Architecture support
--------------------
S390 general architecture support
M: Thomas Huth <thuth@redhat.com>
S: Supported
F: configs/devices/s390x-softmmu/default.mak
F: gdb-xml/s390*.xml
F: hw/char/sclp*.[hc]
F: hw/char/terminal3270.c
F: hw/intc/s390_flic.c
F: hw/intc/s390_flic_kvm.c
F: hw/s390x/
s390x/vfio: ap: Introduce VFIO AP device Introduces a VFIO based AP device. The device is defined via the QEMU command line by specifying: -device vfio-ap,sysfsdev=<path-to-mediated-matrix-device> There may be only one vfio-ap device configured for a guest. The mediated matrix device is created by the VFIO AP device driver by writing a UUID to a sysfs attribute file (see docs/vfio-ap.txt). The mediated matrix device will be named after the UUID. Symbolic links to the $uuid are created in many places, so the path to the mediated matrix device $uuid can be specified in any of the following ways: /sys/devices/vfio_ap/matrix/$uuid /sys/devices/vfio_ap/matrix/mdev_supported_types/vfio_ap-passthrough/devices/$uuid /sys/bus/mdev/devices/$uuid /sys/bus/mdev/drivers/vfio_mdev/$uuid When the vfio-ap device is realized, it acquires and opens the VFIO iommu group to which the mediated matrix device is bound. This causes a VFIO group notification event to be signaled. The vfio_ap device driver's group notification handler will get called at which time the device driver will configure the the AP devices to which the guest will be granted access. Signed-off-by: Tony Krowiak <akrowiak@linux.ibm.com> Tested-by: Pierre Morel <pmorel@linux.ibm.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Tested-by: Pierre Morel <pmorel@linux.ibm.com> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20181010170309.12045-6-akrowiak@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [CH: added missing g_free and device category] Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-10-10 20:03:07 +03:00
F: hw/vfio/ap.c
F: hw/vfio/ccw.c
F: hw/watchdog/wdt_diag288.c
F: include/hw/s390x/
F: include/hw/watchdog/wdt_diag288.h
F: pc-bios/s390-ccw/
F: pc-bios/s390-ccw.img
F: target/s390x/
F: docs/system/target-s390x.rst
F: docs/system/s390x/
F: tests/migration/s390x/
K: ^Subject:.*(?i)s390x?
L: qemu-s390x@nongnu.org
MIPS general architecture support
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Odd Fixes
K: ^Subject:.*(?i)mips
F: docs/system/target-mips.rst
F: configs/targets/mips*
X86 general architecture support
M: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: configs/devices/i386-softmmu/default.mak
F: configs/targets/i386-softmmu.mak
F: configs/targets/x86_64-softmmu.mak
F: docs/system/target-i386*
F: target/i386/*.[ch]
F: target/i386/Kconfig
F: target/i386/meson.build
F: tools/i386/
Guest CPU cores (TCG)
---------------------
Overall TCG CPUs
M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
S: Maintained
F: system/cpus.c
F: system/watchpoint.c
F: cpu-common.c
F: cpu-target.c
F: page-vary-target.c
exec: Build page-vary-common.c with -fno-lto In bbc17caf81f, we used an alias attribute to allow target_page to be declared const, and yet be initialized late. This fails when using LTO with several versions of gcc. The compiler looks through the alias and decides that the const variable is statically initialized to zero, then propagates that zero to many uses of the variable. This can be avoided by compiling one object file with -fno-lto. In this way, any initializer cannot be seen, and the constant propagation does not occur. Since we are certain to have this separate compilation unit, we can drop the alias attribute as well. We simply have differing declarations for target_page in different compilation units. Drop the use of init_target_page, and drop the configure detection for CONFIG_ATTRIBUTE_ALIAS. In order to change the compilation flags for a file with meson, we must use a static_library. This runs into specific_ss, where we would need to create many static_library instances. Fix this by splitting page-vary.c: the page-vary-common.c part is compiled once as a static_library, while the page-vary.c part is left in specific_ss in order to handle the target-specific value of TARGET_PAGE_BITS_MIN. Reported-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210321211534.2101231-1-richard.henderson@linaro.org> [PMD: Fix typo in subject, split original patch in 3] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Gavin Shan <gshan@redhat.com> Message-Id: <20210322112427.4045204-4-f4bug@amsat.org> [rth: Update MAINTAINERS] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-22 14:24:26 +03:00
F: page-vary-common.c
F: accel/tcg/
F: accel/stubs/tcg-stub.c
F: util/cacheinfo.c
F: util/cacheflush.c
F: scripts/decodetree.py
F: docs/devel/decodetree.rst
F: docs/devel/tcg*
F: include/exec/cpu*.h
F: include/exec/exec-all.h
F: include/exec/tb-flush.h
F: include/exec/target_long.h
F: include/exec/helper*.h
F: include/exec/helper*.h.inc
F: include/exec/helper-info.c.inc
F: include/exec/page-protection.h
F: include/sysemu/cpus.h
F: include/sysemu/tcg.h
F: include/hw/core/tcg-cpu-ops.h
F: host/include/*/host/cpuinfo.h
F: util/cpuinfo-*.c
F: include/tcg/
F: tests/decode/
FPU emulation
M: Aurelien Jarno <aurelien@aurel32.net>
M: Peter Maydell <peter.maydell@linaro.org>
M: Alex Bennée <alex.bennee@linaro.org>
S: Maintained
F: fpu/
F: include/fpu/
F: tests/fp/
Alpha TCG CPUs
M: Richard Henderson <richard.henderson@linaro.org>
S: Maintained
F: target/alpha/
F: tests/tcg/alpha/
F: disas/alpha.c
ARM TCG CPUs
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Maintained
F: target/arm/
F: target/arm/tcg/
F: tests/tcg/arm/
F: tests/tcg/aarch64/
F: tests/qtest/arm-cpu-features.c
F: hw/arm/
F: hw/cpu/a*mpcore.c
F: include/hw/cpu/a*mpcore.h
docs/system: Split target-arm.rst into sub-documents Currently the documentation for Arm system emulator targets is in a single target-arm.rst. This describes only some of the boards and often in a fairly abbreviated fashion. Restructure it so that each board has its own documentation file in the docs/system/arm/ subdirectory. This will hopefully encourage us to write board documentation that describes the board in detail, rather than a few brief paragraphs in a single long page. The table of contents should also help users to find the board they care about faster. Once the structure is in place we'll be able to move microvm.rst from the top-level docs/ directory. All the text from the old page is retained, except for the final paragraph ("A Linux 2.6 test image is available on the QEMU web site. More information is available in the QEMU mailing-list archive."), which is deleted. The git history shows this was originally added in reference to the integratorcp board (at that time the only Arm board that was supported), and has subsequently gradually been further and further separated from the integratorcp documentation by the insertion of other board documentation sections. It's extremely out of date and no longer accurate, since AFAICT there isn't an integratorcp kernel on the website any more; so better deleted than retained. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200309215818.2021-3-peter.maydell@linaro.org
2020-03-10 00:58:15 +03:00
F: docs/system/target-arm.rst
F: docs/system/arm/cpu-features.rst
ARM SMMU
M: Eric Auger <eric.auger@redhat.com>
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/smmu*
F: include/hw/arm/smmu*
F: tests/avocado/smmu.py
AVR TCG CPUs
M: Michael Rolnik <mrolnik@gmail.com>
S: Maintained
F: docs/system/target-avr.rst
F: gdb-xml/avr-cpu.xml
F: target/avr/
F: tests/avocado/machine_avr6.py
CRIS TCG CPUs
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
S: Maintained
F: target/cris/
F: hw/cris/
F: include/hw/cris/
F: tests/tcg/cris/
F: disas/cris.c
Hexagon TCG CPUs
M: Brian Cain <bcain@quicinc.com>
S: Supported
F: target/hexagon/
X: target/hexagon/idef-parser/
X: target/hexagon/gen_idef_parser_funcs.py
F: linux-user/hexagon/
F: tests/tcg/hexagon/
F: disas/hexagon.c
F: configs/targets/hexagon-linux-user/default.mak
F: docker/dockerfiles/debian-hexagon-cross.docker
F: gdb-xml/hexagon*.xml
Hexagon idef-parser
M: Alessandro Di Federico <ale@rev.ng>
M: Anton Johansson <anjo@rev.ng>
S: Supported
F: target/hexagon/idef-parser/
F: target/hexagon/gen_idef_parser_funcs.py
HPPA (PA-RISC) TCG CPUs
M: Richard Henderson <richard.henderson@linaro.org>
S: Maintained
F: target/hppa/
F: disas/hppa.c
F: tests/tcg/hppa/
LoongArch TCG CPUs
M: Song Gao <gaosong@loongson.cn>
S: Maintained
F: target/loongarch/
F: tests/tcg/loongarch64/
F: tests/avocado/machine_loongarch.py
M68K TCG CPUs
M: Laurent Vivier <laurent@vivier.eu>
S: Maintained
F: target/m68k/
F: disas/m68k.c
F: tests/tcg/m68k/
MicroBlaze TCG CPUs
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
S: Maintained
F: target/microblaze/
F: hw/microblaze/
F: disas/microblaze.c
F: tests/docker/dockerfiles/debian-microblaze-cross.d/build-toolchain.sh
MIPS TCG CPUs
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Aurelien Jarno <aurelien@aurel32.net>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
R: Aleksandar Rikalo <arikalo@gmail.com>
S: Odd Fixes
F: target/mips/
F: disas/*mips.c
docs/system: Convert qemu-cpu-models.texi to rST This doc was originally written by Daniel P. Berrangé <berrange@redhat.com>, introduced via commit[1]: 2544e9e4aa (docs: add guidance on configuring CPU models for x86, 2018-06-27). In this patch: - 1-1 conversion of Texinfo to rST, besides a couple of minor tweaks that are too trivial to mention. (Thanks to Stephen Finucane on IRC for the suggestion to use rST "definition lists" instead of bullets in some places.) Further modifications will be done via a separate patch. - rST and related infra changes: manual page generation, Makefile fixes, clean up references to qemu-cpu-models.texi, update year in the copyright notice, etc. [1] https://git.qemu.org/?p=qemu.git;a=commit;h=2544e9e4aa As part of the conversion, we use a more generic 'author' attribution for the manpage than we previously had, as agreed with the original author Dan Berrange. Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200228153619.9906-16-peter.maydell@linaro.org Message-id: 20200226113034.6741-15-pbonzini@redhat.com [Move macros to defs.rst.inc, split in x86 and MIPS parts, make qemu-cpu-models.rst a standalone document. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [PMM: Move defs.rst.inc setup to its own commit; fix minor issues with MAINTAINERS file updates; drop copyright date change; keep capitalization of "QEMU Project developers" consistent with other uses; minor Makefile fixups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28 18:36:01 +03:00
F: docs/system/cpu-models-mips.rst.inc
F: tests/tcg/mips/
OpenRISC TCG CPUs
M: Stafford Horne <shorne@gmail.com>
S: Odd Fixes
F: docs/system/openrisc/cpu-features.rst
F: target/openrisc/
F: hw/openrisc/
F: include/hw/openrisc/
F: tests/tcg/openrisc/
PowerPC TCG CPUs
2023-09-15 14:05:07 +03:00
M: Nicholas Piggin <npiggin@gmail.com>
M: Daniel Henrique Barboza <danielhb413@gmail.com>
L: qemu-ppc@nongnu.org
S: Odd Fixes
F: target/ppc/
F: hw/ppc/ppc.c
F: hw/ppc/ppc_booke.c
F: include/hw/ppc/ppc.h
F: hw/ppc/meson.build
F: hw/ppc/trace*
F: configs/devices/ppc*
F: docs/system/ppc/embedded.rst
F: docs/system/target-ppc.rst
F: tests/tcg/ppc*/*
RISC-V TCG CPUs
M: Palmer Dabbelt <palmer@dabbelt.com>
M: Alistair Francis <alistair.francis@wdc.com>
M: Bin Meng <bmeng.cn@gmail.com>
R: Weiwei Li <liwei1518@gmail.com>
R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
L: qemu-riscv@nongnu.org
S: Supported
F: configs/targets/riscv*
F: docs/system/target-riscv.rst
F: target/riscv/
F: hw/riscv/
F: hw/intc/riscv*
F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
F: tests/tcg/riscv64/
RISC-V XThead* extensions
M: Christoph Muellner <christoph.muellner@vrull.eu>
M: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
L: qemu-riscv@nongnu.org
S: Supported
F: target/riscv/insn_trans/trans_xthead.c.inc
F: target/riscv/xthead*.decode
F: target/riscv/th_*
F: disas/riscv-xthead*
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
L: qemu-riscv@nongnu.org
S: Maintained
F: target/riscv/XVentanaCondOps.decode
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
F: disas/riscv-xventana*
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
S: Orphan
F: target/rx/
S390 TCG CPUs
M: Richard Henderson <richard.henderson@linaro.org>
M: David Hildenbrand <david@redhat.com>
R: Ilya Leoshkevich <iii@linux.ibm.com>
S: Maintained
F: target/s390x/
F: target/s390x/tcg
F: hw/s390x/
F: tests/tcg/s390x/
L: qemu-s390x@nongnu.org
SH4 TCG CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
S: Orphan
F: target/sh4/
F: hw/sh4/
F: disas/sh4.c
F: include/hw/sh4/
F: tests/tcg/sh4/
SPARC TCG CPUs
M: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
M: Artyom Tarasenko <atar4qemu@gmail.com>
S: Maintained
F: target/sparc/
F: hw/sparc/
F: hw/sparc64/
F: include/hw/sparc/sparc64.h
F: disas/sparc.c
F: tests/tcg/sparc64/
X86 TCG CPUs
M: Paolo Bonzini <pbonzini@redhat.com>
M: Richard Henderson <richard.henderson@linaro.org>
M: Eduardo Habkost <eduardo@habkost.net>
S: Maintained
F: target/i386/tcg/
F: tests/tcg/i386/
F: tests/tcg/x86_64/
F: hw/i386/
F: docs/system/i386/cpu.rst
F: docs/system/cpu-models-x86*
T: git https://gitlab.com/ehabkost/qemu.git x86-next
Xtensa TCG CPUs
M: Max Filippov <jcmvbkbc@gmail.com>
W: http://wiki.osll.ru/doku.php?id=etc:users:jcmvbkbc:qemu-target-xtensa
S: Maintained
F: target/xtensa/
F: hw/xtensa/
F: tests/tcg/xtensa/
F: tests/tcg/xtensaeb/
F: disas/xtensa.c
F: include/hw/xtensa/xtensa-isa.h
F: configs/devices/xtensa*/default.mak
TriCore TCG CPUs
M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
S: Maintained
F: target/tricore/
F: hw/tricore/
F: include/hw/tricore/
F: tests/tcg/tricore/
Multiarch Linux User Tests
M: Alex Bennée <alex.bennee@linaro.org>
S: Maintained
F: tests/tcg/multiarch/
Guest CPU Cores (KVM)
---------------------
Overall KVM CPUs
M: Paolo Bonzini <pbonzini@redhat.com>
L: kvm@vger.kernel.org
S: Supported
F: */*/kvm*