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target/avr: CPU class: Add GDB support
This includes GDB hooks for reading from wnd wrtiting to AVR registers, and xml register definition file as well. [AM: Split a larger AVR introduction patch into logical units] Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Co-developed-by: Michael Rolnik <mrolnik@gmail.com> Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Michael Rolnik <mrolnik@gmail.com> Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [thuth: Fixed avr_cpu_gdb_read_register() parameter] Signed-off-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20200705140315.260514-7-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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@ -171,6 +171,7 @@ AVR TCG CPUs
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M: Michael Rolnik <mrolnik@gmail.com>
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R: Sarah Harris <S.E.Harris@kent.ac.uk>
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S: Maintained
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F: gdb-xml/avr-cpu.xml
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F: target/avr/
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CRIS TCG CPUs
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49
gdb-xml/avr-cpu.xml
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49
gdb-xml/avr-cpu.xml
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@ -0,0 +1,49 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!-- Register numbers are hard-coded in order to maintain backward
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compatibility with older versions of tools that didn't use xml
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register descriptions. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.riscv.cpu">
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<reg name="r0" bitsize="8" type="int" regnum="0"/>
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<reg name="r1" bitsize="8" type="int"/>
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<reg name="r2" bitsize="8" type="int"/>
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<reg name="r3" bitsize="8" type="int"/>
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<reg name="r4" bitsize="8" type="int"/>
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<reg name="r5" bitsize="8" type="int"/>
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<reg name="r6" bitsize="8" type="int"/>
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<reg name="r7" bitsize="8" type="int"/>
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<reg name="r8" bitsize="8" type="int"/>
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<reg name="r9" bitsize="8" type="int"/>
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<reg name="r10" bitsize="8" type="int"/>
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<reg name="r11" bitsize="8" type="int"/>
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<reg name="r12" bitsize="8" type="int"/>
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<reg name="r13" bitsize="8" type="int"/>
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<reg name="r14" bitsize="8" type="int"/>
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<reg name="r15" bitsize="8" type="int"/>
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<reg name="r16" bitsize="8" type="int"/>
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<reg name="r17" bitsize="8" type="int"/>
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<reg name="r18" bitsize="8" type="int"/>
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<reg name="r19" bitsize="8" type="int"/>
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<reg name="r20" bitsize="8" type="int"/>
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<reg name="r21" bitsize="8" type="int"/>
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<reg name="r22" bitsize="8" type="int"/>
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<reg name="r23" bitsize="8" type="int"/>
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<reg name="r24" bitsize="8" type="int"/>
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<reg name="r25" bitsize="8" type="int"/>
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<reg name="r26" bitsize="8" type="int"/>
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<reg name="r27" bitsize="8" type="int"/>
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<reg name="r28" bitsize="8" type="int"/>
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<reg name="r29" bitsize="8" type="int"/>
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<reg name="r30" bitsize="8" type="int"/>
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<reg name="r31" bitsize="8" type="int"/>
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<reg name="sreg" bitsize="8" type="int"/>
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<reg name="sp" bitsize="8" type="int"/>
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<reg name="pc" bitsize="8" type="int"/>
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</feature>
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@ -210,4 +210,8 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
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cc->disas_set_info = avr_cpu_disas_set_info;
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cc->tcg_initialize = avr_cpu_tcg_init;
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cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
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cc->gdb_read_register = avr_cpu_gdb_read_register;
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cc->gdb_write_register = avr_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 35;
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cc->gdb_core_xml_file = "avr-cpu.xml";
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}
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@ -123,6 +123,8 @@ extern const struct VMStateDescription vms_avr_cpu;
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void avr_cpu_do_interrupt(CPUState *cpu);
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bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
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hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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#define cpu_list avr_cpu_list
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#define cpu_signal_handler cpu_avr_signal_handler
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84
target/avr/gdbstub.c
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84
target/avr/gdbstub.c
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@ -0,0 +1,84 @@
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/*
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* QEMU AVR gdbstub
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*
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* Copyright (c) 2016-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "exec/gdbstub.h"
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int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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/* R */
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if (n < 32) {
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return gdb_get_reg8(mem_buf, env->r[n]);
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}
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/* SREG */
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if (n == 32) {
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uint8_t sreg = cpu_get_sreg(env);
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return gdb_get_reg8(mem_buf, sreg);
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}
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/* SP */
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if (n == 33) {
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return gdb_get_reg16(mem_buf, env->sp & 0x0000ffff);
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}
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/* PC */
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if (n == 34) {
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return gdb_get_reg32(mem_buf, env->pc_w * 2);
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}
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return 0;
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}
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int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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/* R */
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if (n < 32) {
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env->r[n] = *mem_buf;
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return 1;
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}
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/* SREG */
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if (n == 32) {
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cpu_set_sreg(env, *mem_buf);
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return 1;
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}
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/* SP */
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if (n == 33) {
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env->sp = lduw_p(mem_buf);
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return 2;
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}
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/* PC */
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if (n == 34) {
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env->pc_w = ldl_p(mem_buf) / 2;
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return 4;
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}
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return 0;
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}
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