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target/arm: Factor out code for setting MTE TCF0 field
Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20240628050850.536447-7-gustavo.romero@linaro.org> [AJB: clean-up includes, move MTE defines] Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-36-alex.bennee@linaro.org>
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@ -9,3 +9,5 @@ vdso_le_inc = gen_vdso.process('vdso-le.so',
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extra_args: ['-r', '__kernel_rt_sigreturn'])
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linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [vdso_be_inc, vdso_le_inc])
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linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [files('mte_user_helper.c')])
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35
linux-user/aarch64/mte_user_helper.c
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35
linux-user/aarch64/mte_user_helper.c
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@ -0,0 +1,35 @@
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/*
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* ARM MemTag convenience functions.
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "mte_user_helper.h"
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void arm_set_mte_tcf0(CPUArchState *env, abi_long value)
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{
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/*
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* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
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*
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* The kernel has a per-cpu configuration for the sysadmin,
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* /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
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* which qemu does not implement.
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*
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* Because there is no performance difference between the modes, and
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* because SYNC is most useful for debugging MTE errors, choose SYNC
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* as the preferred mode. With this preference, and the way the API
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* uses only two bits, there is no way for the program to select
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* ASYMM mode.
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*/
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unsigned tcf = 0;
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if (value & PR_MTE_TCF_SYNC) {
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tcf = 1;
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} else if (value & PR_MTE_TCF_ASYNC) {
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tcf = 2;
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}
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env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
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}
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32
linux-user/aarch64/mte_user_helper.h
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32
linux-user/aarch64/mte_user_helper.h
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@ -0,0 +1,32 @@
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/*
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* ARM MemTag convenience functions.
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: LGPL-2.1-or-later
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*/
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#ifndef AARCH64_MTE_USER_HELPER_H
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#define AARCH64_MTE USER_HELPER_H
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#ifndef PR_MTE_TCF_SHIFT
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# define PR_MTE_TCF_SHIFT 1
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# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TAG_SHIFT 3
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# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
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#endif
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/**
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* arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register
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* @env: The CPU environment
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* @value: The value to be set for the Tag Check Fault in EL0 field.
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*
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* Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the SYNC
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* mode is selected instead. So, there is no way to set the ASYMM mode.
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*/
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void arm_set_mte_tcf0(CPUArchState *env, abi_long value);
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#endif /* AARCH64_MTE_USER_HELPER_H */
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@ -7,6 +7,7 @@
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#define AARCH64_TARGET_PRCTL_H
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#include "target/arm/cpu-features.h"
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#include "mte_user_helper.h"
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static abi_long do_prctl_sve_get_vl(CPUArchState *env)
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{
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@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
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env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
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if (cpu_isar_feature(aa64_mte, cpu)) {
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/*
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* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
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*
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* The kernel has a per-cpu configuration for the sysadmin,
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* /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
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* which qemu does not implement.
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*
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* Because there is no performance difference between the modes, and
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* because SYNC is most useful for debugging MTE errors, choose SYNC
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* as the preferred mode. With this preference, and the way the API
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* uses only two bits, there is no way for the program to select
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* ASYMM mode.
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*/
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unsigned tcf = 0;
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if (arg2 & PR_MTE_TCF_SYNC) {
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tcf = 1;
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} else if (arg2 & PR_MTE_TCF_ASYNC) {
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tcf = 2;
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}
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env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
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arm_set_mte_tcf0(env, arg2);
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/*
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* Write PR_MTE_TAG to GCR_EL1[Exclude].
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@ -6281,15 +6281,6 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
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# define PR_GET_TAGGED_ADDR_CTRL 56
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# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
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#endif
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#ifndef PR_MTE_TCF_SHIFT
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# define PR_MTE_TCF_SHIFT 1
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# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
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# define PR_MTE_TAG_SHIFT 3
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# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
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#endif
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#ifndef PR_SET_IO_FLUSHER
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# define PR_SET_IO_FLUSHER 57
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# define PR_GET_IO_FLUSHER 58
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