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target/arm: Use correct GDB XML for M-profile cores
GDB's remote protocol requires M-profile cores to use the feature name 'org.gnu.gdb.arm.m-profile' instead of the 'org.gnu.gdb.arm.core' feature used for A- and R-profile cores. We weren't doing this, which meant GDB treated our M-profile cores like A-profile ones. This mostly doesn't matter, but for instance means that it doesn't correctly handle backtraces where an M-profile exception frame is involved. Ship a copy of GDB's arm-m-profile.xml and use it on the M-profile cores. The integer registers have the same offsets as the arm-core.xml, but register 25 is the M-profile XPSR rather than the A-profile CPSR, so we need to update arm_cpu_gdb_read_register() and arm_cpu_gdb_write_register() to handle XSPR reads and writes. Fixes: https://bugs.launchpad.net/qemu/+bug/1877136 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200507134755.13997-1-peter.maydell@linaro.org
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4
configure
vendored
4
configure
vendored
@ -7806,14 +7806,14 @@ case "$target_name" in
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TARGET_SYSTBL_ABI=common,oabi
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bflt="yes"
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mttcg="yes"
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gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"
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gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml arm-m-profile.xml"
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;;
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aarch64|aarch64_be)
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TARGET_ARCH=aarch64
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TARGET_BASE_ARCH=arm
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bflt="yes"
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mttcg="yes"
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gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml"
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gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml arm-m-profile.xml"
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;;
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cris)
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;;
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27
gdb-xml/arm-m-profile.xml
Normal file
27
gdb-xml/arm-m-profile.xml
Normal file
@ -0,0 +1,27 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2010-2020 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.arm.m-profile">
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<reg name="r0" bitsize="32"/>
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<reg name="r1" bitsize="32"/>
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<reg name="r2" bitsize="32"/>
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<reg name="r3" bitsize="32"/>
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<reg name="r4" bitsize="32"/>
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<reg name="r5" bitsize="32"/>
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<reg name="r6" bitsize="32"/>
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<reg name="r7" bitsize="32"/>
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<reg name="r8" bitsize="32"/>
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<reg name="r9" bitsize="32"/>
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<reg name="r10" bitsize="32"/>
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<reg name="r11" bitsize="32"/>
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<reg name="r12" bitsize="32"/>
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<reg name="sp" bitsize="32" type="data_ptr"/>
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<reg name="lr" bitsize="32"/>
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<reg name="pc" bitsize="32" type="code_ptr"/>
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<reg name="xpsr" bitsize="32" regnum="25"/>
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</feature>
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@ -605,6 +605,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
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#endif
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cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
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cc->gdb_core_xml_file = "arm-m-profile.xml";
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}
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static const ARMCPUInfo arm_tcg_cpus[] = {
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@ -57,8 +57,12 @@ int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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}
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return gdb_get_reg32(mem_buf, 0);
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case 25:
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/* CPSR */
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return gdb_get_reg32(mem_buf, cpsr_read(env));
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/* CPSR, or XPSR for M-profile */
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if (arm_feature(env, ARM_FEATURE_M)) {
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return gdb_get_reg32(mem_buf, xpsr_read(env));
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} else {
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return gdb_get_reg32(mem_buf, cpsr_read(env));
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}
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}
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/* Unknown register. */
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return 0;
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@ -98,8 +102,18 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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}
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return 4;
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case 25:
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/* CPSR */
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cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
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/* CPSR, or XPSR for M-profile */
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if (arm_feature(env, ARM_FEATURE_M)) {
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/*
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* Don't allow writing to XPSR.Exception as it can cause
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* a transition into or out of handler mode (it's not
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* writeable via the MSR insn so this is a reasonable
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* restriction). Other fields are safe to update.
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*/
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xpsr_write(env, tmp, ~XPSR_EXCP);
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} else {
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cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
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}
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return 4;
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}
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/* Unknown register. */
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