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target/riscv: honour show_opcodes when disassembling
This makes the output suitable when used for plugins. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-30-alex.bennee@linaro.org>
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f6e0eabdb4
commit
db7e8b1f75
@ -5192,19 +5192,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
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}
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}
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switch (len) {
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case 2:
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(*info->fprintf_func)(info->stream, INST_FMT_2, inst);
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break;
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case 4:
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(*info->fprintf_func)(info->stream, INST_FMT_4, inst);
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break;
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case 6:
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(*info->fprintf_func)(info->stream, INST_FMT_6, inst);
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break;
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default:
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(*info->fprintf_func)(info->stream, INST_FMT_8, inst);
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break;
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if (info->show_opcodes) {
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switch (len) {
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case 2:
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(*info->fprintf_func)(info->stream, INST_FMT_2, inst);
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break;
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case 4:
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(*info->fprintf_func)(info->stream, INST_FMT_4, inst);
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break;
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case 6:
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(*info->fprintf_func)(info->stream, INST_FMT_6, inst);
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break;
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default:
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(*info->fprintf_func)(info->stream, INST_FMT_8, inst);
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break;
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}
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}
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disasm_inst(buf, sizeof(buf), isa, memaddr, inst,
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