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hw/acpi: Update CPUs AML with cpu-(ctrl)dev change
CPUs Control device(\\_SB.PCI0) register interface for the x86 arch is IO port based and existing CPUs AML code assumes _CRS objects would evaluate to a system resource which describes IO Port address. But on ARM arch CPUs control device(\\_SB.PRES) register interface is memory-mapped hence _CRS object should evaluate to system resource which describes memory-mapped base address. Update build CPUs AML function to accept both IO/MEMORY region spaces and accordingly update the _CRS object. Co-developed-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Tested-by: Vishnu Pajjuri <vishnu@os.amperecomputing.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Xianglai Li <lixianglai@loongson.cn> Tested-by: Miguel Luis <miguel.luis@oracle.com> Reviewed-by: Shaoqin Huang <shahuang@redhat.com> Tested-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240716111502.202344-6-salil.mehta@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -338,9 +338,10 @@ const VMStateDescription vmstate_cpu_hotplug = {
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#define CPU_FW_EJECT_EVENT "CEJF"
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void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
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build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
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build_madt_cpu_fn build_madt_cpu, hwaddr base_addr,
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const char *res_root,
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const char *event_handler_method)
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const char *event_handler_method,
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AmlRegionSpace rs)
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{
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Aml *ifctx;
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Aml *field;
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@ -364,14 +365,22 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
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aml_name_decl("_UID", aml_string("CPU Hotplug resources")));
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aml_append(cpu_ctrl_dev, aml_mutex(CPU_LOCK, 0));
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assert((rs == AML_SYSTEM_IO) || (rs == AML_SYSTEM_MEMORY));
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crs = aml_resource_template();
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aml_append(crs, aml_io(AML_DECODE16, io_base, io_base, 1,
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if (rs == AML_SYSTEM_IO) {
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aml_append(crs, aml_io(AML_DECODE16, base_addr, base_addr, 1,
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ACPI_CPU_HOTPLUG_REG_LEN));
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} else if (rs == AML_SYSTEM_MEMORY) {
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aml_append(crs, aml_memory32_fixed(base_addr,
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ACPI_CPU_HOTPLUG_REG_LEN, AML_READ_WRITE));
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}
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aml_append(cpu_ctrl_dev, aml_name_decl("_CRS", crs));
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/* declare CPU hotplug MMIO region with related access fields */
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aml_append(cpu_ctrl_dev,
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aml_operation_region("PRST", AML_SYSTEM_IO, aml_int(io_base),
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aml_operation_region("PRST", rs, aml_int(base_addr),
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ACPI_CPU_HOTPLUG_REG_LEN));
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field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK,
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@ -1536,7 +1536,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
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.fw_unplugs_cpu = pm->smi_on_cpu_unplug,
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};
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build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
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pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02");
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pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02",
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AML_SYSTEM_IO);
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}
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if (pcms->memhp_io_base && nr_mem) {
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@ -63,9 +63,10 @@ typedef void (*build_madt_cpu_fn)(int uid, const CPUArchIdList *apic_ids,
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GArray *entry, bool force_enabled);
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void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
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build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
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build_madt_cpu_fn build_madt_cpu, hwaddr base_addr,
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const char *res_root,
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const char *event_handler_method);
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const char *event_handler_method,
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AmlRegionSpace rs);
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void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list);
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