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@ -29,6 +29,7 @@ TSS2_RC (*sym_Esys_GetCapability)(ESYS_CONTEXT *esysContext, ESYS_TR shandle1, E
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TSS2_RC (*sym_Esys_GetRandom)(ESYS_CONTEXT *esysContext, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, UINT16 bytesRequested, TPM2B_DIGEST **randomBytes) = NULL;
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TSS2_RC (*sym_Esys_Initialize)(ESYS_CONTEXT **esys_context, TSS2_TCTI_CONTEXT *tcti, TSS2_ABI_VERSION *abiVersion) = NULL;
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TSS2_RC (*sym_Esys_Load)(ESYS_CONTEXT *esysContext, ESYS_TR parentHandle, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, const TPM2B_PRIVATE *inPrivate, const TPM2B_PUBLIC *inPublic, ESYS_TR *objectHandle) = NULL;
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TSS2_RC (*sym_Esys_PCR_Read)(ESYS_CONTEXT *esysContext, ESYS_TR shandle1,ESYS_TR shandle2, ESYS_TR shandle3, const TPML_PCR_SELECTION *pcrSelectionIn, UINT32 *pcrUpdateCounter, TPML_PCR_SELECTION **pcrSelectionOut, TPML_DIGEST **pcrValues);
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TSS2_RC (*sym_Esys_PolicyGetDigest)(ESYS_CONTEXT *esysContext, ESYS_TR policySession, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, TPM2B_DIGEST **policyDigest) = NULL;
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TSS2_RC (*sym_Esys_PolicyPCR)(ESYS_CONTEXT *esysContext, ESYS_TR policySession, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, const TPM2B_DIGEST *pcrDigest, const TPML_PCR_SELECTION *pcrs) = NULL;
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TSS2_RC (*sym_Esys_StartAuthSession)(ESYS_CONTEXT *esysContext, ESYS_TR tpmKey, ESYS_TR bind, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, const TPM2B_NONCE *nonceCaller, TPM2_SE sessionType, const TPMT_SYM_DEF *symmetric, TPMI_ALG_HASH authHash, ESYS_TR *sessionHandle) = NULL;
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@ -56,6 +57,7 @@ int dlopen_tpm2(void) {
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DLSYM_ARG(Esys_GetRandom),
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DLSYM_ARG(Esys_Initialize),
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DLSYM_ARG(Esys_Load),
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DLSYM_ARG(Esys_PCR_Read),
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DLSYM_ARG(Esys_PolicyGetDigest),
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DLSYM_ARG(Esys_PolicyPCR),
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DLSYM_ARG(Esys_StartAuthSession),
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@ -381,16 +383,108 @@ static int tpm2_make_primary(
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return 0;
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}
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static void tpm2_pcr_mask_to_selecion(uint32_t mask, uint16_t bank, TPML_PCR_SELECTION *ret) {
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assert(ret);
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/* We only do 24bit here, as that's what PC TPMs are supposed to support */
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assert(mask <= 0xFFFFFFU);
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*ret = (TPML_PCR_SELECTION) {
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.count = 1,
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.pcrSelections[0].hash = bank,
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.pcrSelections[0].sizeofSelect = 3,
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.pcrSelections[0].pcrSelect[0] = mask & 0xFF,
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.pcrSelections[0].pcrSelect[1] = (mask >> 8) & 0xFF,
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.pcrSelections[0].pcrSelect[2] = (mask >> 16) & 0xFF,
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};
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}
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static unsigned find_nth_bit(uint32_t mask, unsigned n) {
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uint32_t bit = 1;
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assert(n < 32);
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/* Returns the bit index of the nth set bit, e.g. mask=0b101001, n=3 → 5 */
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for (unsigned i = 0; i < sizeof(mask)*8; i++) {
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if (bit & mask) {
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if (n == 0)
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return i;
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n--;
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}
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bit <<= 1;
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}
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return UINT_MAX;
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}
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static int tpm2_pcr_mask_good(
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ESYS_CONTEXT *c,
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TPMI_ALG_HASH bank,
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uint32_t mask) {
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_cleanup_(Esys_Freep) TPML_DIGEST *pcr_values = NULL;
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TPML_PCR_SELECTION selection;
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bool good = false;
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TSS2_RC rc;
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assert(c);
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/* So we have the problem that some systems might have working TPM2 chips, but the firmware doesn't
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* actually measure into them, or only into a suboptimal bank. If so, the PCRs should be all zero or
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* all 0xFF. Detect that, so that we can warn and maybe pick a better bank. */
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tpm2_pcr_mask_to_selecion(mask, bank, &selection);
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rc = sym_Esys_PCR_Read(
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c,
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ESYS_TR_NONE,
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ESYS_TR_NONE,
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ESYS_TR_NONE,
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&selection,
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NULL,
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NULL,
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&pcr_values);
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if (rc != TSS2_RC_SUCCESS)
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return log_error_errno(SYNTHETIC_ERRNO(ENOTRECOVERABLE),
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"Failed to read TPM2 PCRs: %s", sym_Tss2_RC_Decode(rc));
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/* If at least one of the selected PCR values is something other than all 0x00 or all 0xFF we are happy. */
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for (unsigned i = 0; i < pcr_values->count; i++) {
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if (DEBUG_LOGGING) {
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_cleanup_free_ char *h = NULL;
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unsigned j;
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h = hexmem(pcr_values->digests[i].buffer, pcr_values->digests[i].size);
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j = find_nth_bit(mask, i);
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assert(j != UINT_MAX);
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log_debug("PCR %u value: %s", j, strna(h));
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}
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if (!memeqbyte(0x00, pcr_values->digests[i].buffer, pcr_values->digests[i].size) &&
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!memeqbyte(0xFF, pcr_values->digests[i].buffer, pcr_values->digests[i].size))
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good = true;
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}
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return good;
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}
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static int tpm2_get_best_pcr_bank(
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ESYS_CONTEXT *c,
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uint32_t pcr_mask,
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TPMI_ALG_HASH *ret) {
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_cleanup_(Esys_Freep) TPMS_CAPABILITY_DATA *pcap = NULL;
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TPMI_ALG_HASH hash = TPM2_ALG_SHA1;
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bool found = false;
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TPMI_ALG_HASH supported_hash = 0, hash_with_valid_pcr = 0;
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TPMI_YES_NO more;
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TSS2_RC rc;
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assert(c);
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rc = sym_Esys_GetCapability(
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c,
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ESYS_TR_NONE,
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@ -409,6 +503,11 @@ static int tpm2_get_best_pcr_bank(
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for (size_t i = 0; i < pcap->data.assignedPCR.count; i++) {
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bool valid = true;
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int good;
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/* For now we are only interested in the SHA1 and SHA256 banks */
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if (!IN_SET(pcap->data.assignedPCR.pcrSelections[i].hash, TPM2_ALG_SHA256, TPM2_ALG_SHA1))
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continue;
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/* As per
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* https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05_v23_pub.pdf a
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@ -436,28 +535,58 @@ static int tpm2_get_best_pcr_bank(
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continue;
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}
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if (pcap->data.assignedPCR.pcrSelections[i].hash == TPM2_ALG_SHA256) {
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hash = TPM2_ALG_SHA256;
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found = true;
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break;
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}
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good = tpm2_pcr_mask_good(c, pcap->data.assignedPCR.pcrSelections[i].hash, pcr_mask);
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if (good < 0)
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return good;
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if (pcap->data.assignedPCR.pcrSelections[i].hash == TPM2_ALG_SHA1)
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found = true;
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if (pcap->data.assignedPCR.pcrSelections[i].hash == TPM2_ALG_SHA256) {
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supported_hash = TPM2_ALG_SHA256;
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if (good) {
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/* Great, SHA256 is supported and has initialized PCR values, we are done. */
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hash_with_valid_pcr = TPM2_ALG_SHA256;
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break;
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}
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} else {
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assert(pcap->data.assignedPCR.pcrSelections[i].hash == TPM2_ALG_SHA1);
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if (supported_hash == 0)
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supported_hash = TPM2_ALG_SHA1;
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if (good && hash_with_valid_pcr == 0)
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hash_with_valid_pcr = TPM2_ALG_SHA1;
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}
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}
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if (!found)
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/* We preferably pick SHA256, but only if its PCRs are initialized or neither the SHA1 nor the SHA256
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* PCRs are initialized. If SHA256 is not supported but SHA1 is and its PCRs are too, we prefer
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* SHA1.
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*
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* We log at LOG_NOTICE level whenever we end up using the SHA1 bank or when the PCRs we bind to are
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* not initialized. */
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if (hash_with_valid_pcr == TPM2_ALG_SHA256) {
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assert(supported_hash == TPM2_ALG_SHA256);
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log_debug("TPM2 device supports SHA256 PCR bank and SHA256 PCRs are valid, yay!");
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*ret = TPM2_ALG_SHA256;
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} else if (hash_with_valid_pcr == TPM2_ALG_SHA1) {
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if (supported_hash == TPM2_ALG_SHA256)
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log_notice("TPM2 device supports both SHA1 and SHA256 PCR banks, but only SHA1 PCRs are valid, falling back to SHA1 bank. This reduces the security level substantially.");
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else {
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assert(supported_hash == TPM2_ALG_SHA1);
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log_notice("TPM2 device lacks support for SHA256 PCR bank, but SHA1 bank is supported and SHA1 PCRs are valid, falling back to SHA1 bank. This reduces the security level substantially.");
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}
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*ret = TPM2_ALG_SHA1;
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} else if (supported_hash == TPM2_ALG_SHA256) {
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log_notice("TPM2 device supports SHA256 PCR bank but none of the selected PCRs are valid! Firmware apparently did not initialize any of the selected PCRs. Proceeding anyway with SHA256 bank. PCR policy effectively unenforced!");
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*ret = TPM2_ALG_SHA256;
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} else if (supported_hash == TPM2_ALG_SHA1) {
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log_notice("TPM2 device lacks support for SHA256 bank, but SHA1 bank is supported, but none of the selected PCRs are valid! Firmware apparently did not initialize any of the selected PCRs. Proceeding anyway with SHA1 bank. PCR policy effectively unenforced!");
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*ret = TPM2_ALG_SHA1;
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} else
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return log_error_errno(SYNTHETIC_ERRNO(EOPNOTSUPP),
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"TPM2 module supports neither SHA1 nor SHA256 PCR banks, cannot operate.");
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if (hash == TPM2_ALG_SHA256)
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log_debug("TPM2 device supports SHA256 PCR banks, yay!");
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else {
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assert(hash == TPM2_ALG_SHA1);
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log_debug("TPM2 device lacks support for SHA256 PCR banks, falling back to SHA1 banks.");
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}
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*ret = hash;
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return 0;
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}
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@ -478,15 +607,8 @@ static int tpm2_make_pcr_session(
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.aes = TPM2_ALG_CFB,
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}
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};
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TPML_PCR_SELECTION pcr_selection = {
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.count = 1,
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.pcrSelections[0].hash = TPM2_ALG_SHA256, /* overridden below, depending on TPM2 capabilities */
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.pcrSelections[0].sizeofSelect = 3,
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.pcrSelections[0].pcrSelect[0] = pcr_mask & 0xFF,
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.pcrSelections[0].pcrSelect[1] = (pcr_mask >> 8) & 0xFF,
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.pcrSelections[0].pcrSelect[2] = (pcr_mask >> 16) & 0xFF,
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};
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_cleanup_(Esys_Freep) TPM2B_DIGEST *policy_digest = NULL;
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TPML_PCR_SELECTION pcr_selection;
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ESYS_TR session = ESYS_TR_NONE;
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TSS2_RC rc;
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int r;
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@ -496,13 +618,17 @@ static int tpm2_make_pcr_session(
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log_debug("Starting authentication session.");
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if (pcr_bank != UINT16_MAX)
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pcr_selection.pcrSelections[0].hash = pcr_bank;
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tpm2_pcr_mask_to_selecion(pcr_mask, pcr_bank, &pcr_selection);
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else {
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TPMI_ALG_HASH h;
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/* No bank configured, pick automatically. Some TPM2 devices only can do SHA1. If we detect
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* that use that, but preferably use SHA256 */
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r = tpm2_get_best_pcr_bank(c, &pcr_selection.pcrSelections[0].hash);
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r = tpm2_get_best_pcr_bank(c, pcr_mask, &h);
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if (r < 0)
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return r;
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tpm2_pcr_mask_to_selecion(pcr_mask, h, &pcr_selection);
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}
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rc = sym_Esys_StartAuthSession(
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@ -19,6 +19,7 @@ extern TSS2_RC (*sym_Esys_GetCapability)(ESYS_CONTEXT *esysContext, ESYS_TR shan
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extern TSS2_RC (*sym_Esys_GetRandom)(ESYS_CONTEXT *esysContext, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, UINT16 bytesRequested, TPM2B_DIGEST **randomBytes);
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extern TSS2_RC (*sym_Esys_Initialize)(ESYS_CONTEXT **esys_context, TSS2_TCTI_CONTEXT *tcti, TSS2_ABI_VERSION *abiVersion);
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extern TSS2_RC (*sym_Esys_Load)(ESYS_CONTEXT *esysContext, ESYS_TR parentHandle, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, const TPM2B_PRIVATE *inPrivate, const TPM2B_PUBLIC *inPublic, ESYS_TR *objectHandle);
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extern TSS2_RC (*sym_Esys_PCR_Read)(ESYS_CONTEXT *esysContext, ESYS_TR shandle1,ESYS_TR shandle2, ESYS_TR shandle3, const TPML_PCR_SELECTION *pcrSelectionIn, UINT32 *pcrUpdateCounter, TPML_PCR_SELECTION **pcrSelectionOut, TPML_DIGEST **pcrValues);
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extern TSS2_RC (*sym_Esys_PolicyGetDigest)(ESYS_CONTEXT *esysContext, ESYS_TR policySession, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, TPM2B_DIGEST **policyDigest);
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extern TSS2_RC (*sym_Esys_PolicyPCR)(ESYS_CONTEXT *esysContext, ESYS_TR policySession, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, const TPM2B_DIGEST *pcrDigest, const TPML_PCR_SELECTION *pcrs);
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extern TSS2_RC (*sym_Esys_StartAuthSession)(ESYS_CONTEXT *esysContext, ESYS_TR tpmKey, ESYS_TR bind, ESYS_TR shandle1, ESYS_TR shandle2, ESYS_TR shandle3, const TPM2B_NONCE *nonceCaller, TPM2_SE sessionType, const TPMT_SYM_DEF *symmetric, TPMI_ALG_HASH authHash, ESYS_TR *sessionHandle);
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