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git://git.proxmox.com/git/pve-docs.git
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qm: move out known vCPU list to actual appendix
Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
This commit is contained in:
Thomas Lamprecht
parent
0c3c5ff3ab
commit
2157032d7c
@ -319,6 +319,15 @@ include::calendar-events.adoc[]
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:leveloffset: 0
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[appendix]
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QEMU vCPU List
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--------------
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:leveloffset: 1
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include::qm-vcpu-list.adoc[]
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:leveloffset: 0
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[appendix]
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Firewall Macro Definitions
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--------------------------
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108
qm-vcpu-list.adoc
Normal file
108
qm-vcpu-list.adoc
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@ -0,0 +1,108 @@
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[[chapter_qm_vcpu_list]]
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Introduction
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-------------
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This is a list of AMD and Intel x86-64/amd64 CPU types as defined in QEMU,
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going back to 2007.
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Intel CPU Types
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---------------
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https://en.wikipedia.org/wiki/List_of_Intel_Xeon_processors[Intel processors]
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* 'Nahelem' : https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)[1st generation of the Intel Core processor]
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+
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* 'Nahelem-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'Westmere' : https://en.wikipedia.org/wiki/Westmere_(microarchitecture)[1st generation of the Intel Core processor (Xeon E7-)]
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+
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* 'Westmere-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'SandyBridge' : https://en.wikipedia.org/wiki/Sandy_Bridge[2nd generation of the Intel Core processor]
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+
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* 'SandyBridge-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'IvyBridge' : https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)[3rd generation of the Intel Core processor]
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+
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* 'IvyBridge-IBRS (v2)': add Spectre v1 protection ('+spec-ctrl')
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+
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* 'Haswell' : https://en.wikipedia.org/wiki/Haswell_(microarchitecture)[4th generation of the Intel Core processor]
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+
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* 'Haswell-noTSX (v2)' : disable TSX ('-hle', '-rtm')
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+
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* 'Haswell-IBRS (v3)' : re-add TSX, add Spectre v1 protection ('+hle', '+rtm',
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'+spec-ctrl')
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+
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* 'Haswell-noTSX-IBRS (v4)' : disable TSX ('-hle', '-rtm')
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+
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* 'Broadwell': https://en.wikipedia.org/wiki/Broadwell_(microarchitecture)[5th generation of the Intel Core processor]
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+
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* 'Skylake': https://en.wikipedia.org/wiki/Skylake_(microarchitecture)[1st generation Xeon Scalable server processors]
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+
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* 'Skylake-IBRS (v2)' : add Spectre v1 protection, disable CLFLUSHOPT
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('+spec-ctrl', '-clflushopt')
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+
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* 'Skylake-noTSX-IBRS (v3)' : disable TSX ('-hle', '-rtm')
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+
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* 'Skylake-v4': add EPT switching ('+vmx-eptp-switching')
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+
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* 'Cascadelake': https://en.wikipedia.org/wiki/Cascade_Lake_(microprocessor)[2nd generation Xeon Scalable processor]
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+
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* 'Cascadelake-v2' : add arch_capabilities msr ('+arch-capabilities',
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'+rdctl-no', '+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no')
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+
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* 'Cascadelake-v3' : disable TSX ('-hle', '-rtm')
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+
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* 'Cascadelake-v4' : add EPT switching ('+vmx-eptp-switching')
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+
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* 'Cascadelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'Cooperlake' : https://en.wikipedia.org/wiki/Cooper_Lake_(microprocessor)[3rd generation Xeon Scalable processors for 4 & 8 sockets servers]
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+
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* 'Cooperlake-v2' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'Icelake': https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)[3rd generation Xeon Scalable server processors]
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+
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* 'Icelake-v2' : disable TSX ('-hle', '-rtm')
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+
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* 'Icelake-v3' : add arch_capabilities msr ('+arch-capabilities', '+rdctl-no',
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'+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no', '+pschange-mc-no', '+taa-no')
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+
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* 'Icelake-v4' : add missing flags ('+sha-ni', '+avx512ifma', '+rdpid', '+fsrm',
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'+vmx-rdseed-exit', '+vmx-pml', '+vmx-eptp-switching')
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+
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* 'Icelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'Icelake-v6' : add "5-level EPT" ('+vmx-page-walk-5')
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+
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* 'SapphireRapids' : https://en.wikipedia.org/wiki/Sapphire_Rapids[4th generation Xeon Scalable server processors]
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AMD CPU Types
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-------------
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https://en.wikipedia.org/wiki/List_of_AMD_processors[AMD processors]
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* 'Opteron_G3' : https://en.wikipedia.org/wiki/AMD_10h[K10]
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+
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* 'Opteron_G4' : https://en.wikipedia.org/wiki/Bulldozer_(microarchitecture)[Bulldozer]
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+
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* 'Opteron_G5' : https://en.wikipedia.org/wiki/Piledriver_(microarchitecture)[Piledriver]
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+
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* 'EPYC' : https://en.wikipedia.org/wiki/Zen_(first_generation)[1st generation of Zen processors]
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+
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* 'EPYC-IBPB (v2)' : add Spectre v1 protection ('+ibpb')
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+
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* 'EPYC-v3' : add missing flags ('+perfctr-core', '+clzero', '+xsaveerptr',
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'+xsaves')
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+
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* 'EPYC-Rome' : https://en.wikipedia.org/wiki/Zen_2[2nd generation of Zen processors]
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+
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* 'EPYC-Rome-v2' : add Spectre v2, v4 protection ('+ibrs', '+amd-ssbd')
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+
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* 'EPYC-Milan' : https://en.wikipedia.org/wiki/Zen_3[3rd generation of Zen processors]
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+
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* 'EPYC-Milan-v2' : add missing flags ('+vaes', '+vpclmulqdq',
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'+stibp-always-on', '+amd-psfd', '+no-nested-data-bp',
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'+lfence-always-serializing', '+null-sel-clr-base')
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107
qm.adoc
107
qm.adoc
@ -388,7 +388,7 @@ cluster, choose the lowest compatible virtual QEMU CPU type.
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NOTE: Live migrations between Intel and AMD host CPUs have no guarantee to work.
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See also
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xref:qm_amd_intel_cpu_types_list[List of AMD and Intel CPU Types as Defined in QEMU].
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xref:chapter_qm_vcpu_list[List of AMD and Intel CPU Types as Defined in QEMU].
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QEMU CPU Types
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^^^^^^^^^^^^^^
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@ -1823,111 +1823,6 @@ remove such a lock manually (for example after a power failure).
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CAUTION: Only do that if you are sure the action which set the lock is
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no longer running.
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[[qm_amd_intel_cpu_types_list]]
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Appendix: List of AMD and Intel CPU Types as Defined in QEMU
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------------------------------------------------------------
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Intel CPU Types Since 2007 as Defined in QEMU
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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https://en.wikipedia.org/wiki/List_of_Intel_Xeon_processors[Intel processors]
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* 'Nahelem' : https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)[1st generation of the Intel Core processor]
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+
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* 'Nahelem-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'Westmere' : https://en.wikipedia.org/wiki/Westmere_(microarchitecture)[1st generation of the Intel Core processor (Xeon E7-)]
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+
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* 'Westmere-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'SandyBridge' : https://en.wikipedia.org/wiki/Sandy_Bridge[2nd generation of the Intel Core processor]
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+
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* 'SandyBridge-IBRS (v2)' : add Spectre v1 protection ('+spec-ctrl')
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+
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* 'IvyBridge' : https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)[3rd generation of the Intel Core processor]
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+
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* 'IvyBridge-IBRS (v2)': add Spectre v1 protection ('+spec-ctrl')
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+
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* 'Haswell' : https://en.wikipedia.org/wiki/Haswell_(microarchitecture)[4th generation of the Intel Core processor]
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+
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* 'Haswell-noTSX (v2)' : disable TSX ('-hle', '-rtm')
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+
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* 'Haswell-IBRS (v3)' : re-add TSX, add Spectre v1 protection ('+hle', '+rtm',
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'+spec-ctrl')
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+
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* 'Haswell-noTSX-IBRS (v4)' : disable TSX ('-hle', '-rtm')
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+
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* 'Broadwell': https://en.wikipedia.org/wiki/Broadwell_(microarchitecture)[5th generation of the Intel Core processor]
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+
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* 'Skylake': https://en.wikipedia.org/wiki/Skylake_(microarchitecture)[1st generation Xeon Scalable server processors]
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+
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* 'Skylake-IBRS (v2)' : add Spectre v1 protection, disable CLFLUSHOPT
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('+spec-ctrl', '-clflushopt')
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+
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* 'Skylake-noTSX-IBRS (v3)' : disable TSX ('-hle', '-rtm')
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+
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* 'Skylake-v4': add EPT switching ('+vmx-eptp-switching')
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+
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* 'Cascadelake': https://en.wikipedia.org/wiki/Cascade_Lake_(microprocessor)[2nd generation Xeon Scalable processor]
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+
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* 'Cascadelake-v2' : add arch_capabilities msr ('+arch-capabilities',
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'+rdctl-no', '+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no')
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+
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* 'Cascadelake-v3' : disable TSX ('-hle', '-rtm')
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+
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* 'Cascadelake-v4' : add EPT switching ('+vmx-eptp-switching')
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+
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* 'Cascadelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'Cooperlake' : https://en.wikipedia.org/wiki/Cooper_Lake_(microprocessor)[3rd generation Xeon Scalable processors for 4 & 8 sockets servers]
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+
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* 'Cooperlake-v2' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'Icelake': https://en.wikipedia.org/wiki/Ice_Lake_(microprocessor)[3rd generation Xeon Scalable server processors]
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+
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* 'Icelake-v2' : disable TSX ('-hle', '-rtm')
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+
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* 'Icelake-v3' : add arch_capabilities msr ('+arch-capabilities', '+rdctl-no',
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'+ibrs-all', '+skip-l1dfl-vmentry', '+mds-no', '+pschange-mc-no', '+taa-no')
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+
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* 'Icelake-v4' : add missing flags ('+sha-ni', '+avx512ifma', '+rdpid', '+fsrm',
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'+vmx-rdseed-exit', '+vmx-pml', '+vmx-eptp-switching')
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+
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* 'Icelake-v5' : add XSAVES ('+xsaves', '+vmx-xsaves')
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+
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* 'Icelake-v6' : add "5-level EPT" ('+vmx-page-walk-5')
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+
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* 'SapphireRapids' : https://en.wikipedia.org/wiki/Sapphire_Rapids[4th generation Xeon Scalable server processors]
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AMD CPU Types Since 2007 as Defined in QEMU
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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https://en.wikipedia.org/wiki/List_of_AMD_processors[AMD processors]
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* 'Opteron_G3' : https://en.wikipedia.org/wiki/AMD_10h[K10]
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+
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* 'Opteron_G4' : https://en.wikipedia.org/wiki/Bulldozer_(microarchitecture)[Bulldozer]
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+
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* 'Opteron_G5' : https://en.wikipedia.org/wiki/Piledriver_(microarchitecture)[Piledriver]
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+
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* 'EPYC' : https://en.wikipedia.org/wiki/Zen_(first_generation)[1st generation of Zen processors]
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+
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* 'EPYC-IBPB (v2)' : add Spectre v1 protection ('+ibpb')
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+
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* 'EPYC-v3' : add missing flags ('+perfctr-core', '+clzero', '+xsaveerptr',
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'+xsaves')
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+
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* 'EPYC-Rome' : https://en.wikipedia.org/wiki/Zen_2[2nd generation of Zen processors]
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+
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* 'EPYC-Rome-v2' : add Spectre v2, v4 protection ('+ibrs', '+amd-ssbd')
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+
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* 'EPYC-Milan' : https://en.wikipedia.org/wiki/Zen_3[3rd generation of Zen processors]
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+
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* 'EPYC-Milan-v2' : add missing flags ('+vaes', '+vpclmulqdq',
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'+stibp-always-on', '+amd-psfd', '+no-nested-data-bp',
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'+lfence-always-serializing', '+null-sel-clr-base')
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ifdef::wiki[]
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See Also
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