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#
# For a description of the syntax of this configuration file,
# see Documentation/kbuild/kconfig-language.txt.
#
mainmenu "Linux Kernel Configuration"
config ARM
bool
default y
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select HAVE_AOUT
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select HAVE_IDE
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select RTC_LIB
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select SYS_SUPPORTS_APM_EMULATION
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select HAVE_OPROFILE
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select HAVE_ARCH_KGDB
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select HAVE_KPROBES if (!XIP_KERNEL)
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select HAVE_KRETPROBES if (HAVE_KPROBES)
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select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
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select HAVE_GENERIC_DMA_COHERENT
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help
The ARM series is a line of low-power-consumption RISC chip designs
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licensed by ARM Ltd and targeted at embedded applications and
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handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
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manufactured, but legacy ARM-based PC hardware remains popular in
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Europe. There is an ARM Linux project with a web page at
<http://www.arm.linux.org.uk/>.
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config HAVE_PWM
bool
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config SYS_SUPPORTS_APM_EMULATION
bool
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config GENERIC_GPIO
bool
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config GENERIC_TIME
bool
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config GENERIC_CLOCKEVENTS
bool
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config GENERIC_CLOCKEVENTS_BROADCAST
bool
depends on GENERIC_CLOCKEVENTS
default y if SMP && !LOCAL_TIMERS
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config HAVE_TCM
bool
select GENERIC_ALLOCATOR
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config NO_IOPORT
bool
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config EISA
bool
---help---
The Extended Industry Standard Architecture (EISA) bus was
developed as an open alternative to the IBM MicroChannel bus.
The EISA bus provided some of the features of the IBM MicroChannel
bus while maintaining backward compatibility with cards made for
the older ISA bus. The EISA bus saw limited use between 1988 and
1995 when it was made obsolete by the PCI bus.
Say Y here if you are building a kernel for an EISA-based machine.
Otherwise, say N.
config SBUS
bool
config MCA
bool
help
MicroChannel Architecture is found in some IBM PS/2 machines and
laptops. It is a bus system similar to PCI or ISA. See
<file:Documentation/mca.txt> (and especially the web page given
there) before attempting to build an MCA bus kernel.
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config GENERIC_HARDIRQS
bool
default y
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config STACKTRACE_SUPPORT
bool
default y
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config HAVE_LATENCYTOP_SUPPORT
bool
depends on !SMP
default y
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config LOCKDEP_SUPPORT
bool
default y
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config TRACE_IRQFLAGS_SUPPORT
bool
default y
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config HARDIRQS_SW_RESEND
bool
default y
config GENERIC_IRQ_PROBE
bool
default y
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config GENERIC_LOCKBREAK
bool
default y
depends on SMP && PREEMPT
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config RWSEM_GENERIC_SPINLOCK
bool
default y
config RWSEM_XCHGADD_ALGORITHM
bool
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config ARCH_HAS_ILOG2_U32
bool
config ARCH_HAS_ILOG2_U64
bool
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config ARCH_HAS_CPUFREQ
bool
help
Internal node to signify that the ARCH has CPUFREQ support
and that the relevant menu configurations are displayed for
it.
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config GENERIC_HWEIGHT
bool
default y
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config GENERIC_CALIBRATE_DELAY
bool
default y
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config ARCH_MAY_HAVE_PC_FDC
bool
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config ZONE_DMA
bool
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config GENERIC_ISA_DMA
bool
config FIQ
bool
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config ARCH_MTD_XIP
bool
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config GENERIC_HARDIRQS_NO__DO_IRQ
def_bool y
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if OPROFILE
config OPROFILE_ARMV6
def_bool y
depends on CPU_V6 && !SMP
select OPROFILE_ARM11_CORE
config OPROFILE_MPCORE
def_bool y
depends on CPU_V6 && SMP
select OPROFILE_ARM11_CORE
config OPROFILE_ARM11_CORE
bool
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config OPROFILE_ARMV7
def_bool y
depends on CPU_V7 && !SMP
bool
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endif
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config VECTORS_BASE
hex
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default 0xffff0000 if MMU || CPU_HIGH_VECTOR
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default DRAM_BASE if REMAP_VECTORS_TO_RAM
default 0x00000000
help
The base address of exception vectors.
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source "init/Kconfig"
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source "kernel/Kconfig.freezer"
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menu "System Type"
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config MMU
bool "MMU-based Paged Memory Management Support"
default y
help
Select if you want MMU-based virtualised addressing space
support by paged memory management. If unsure, say 'Y'.
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choice
prompt "ARM system type"
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default ARCH_VERSATILE
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config ARCH_AAEC2000
bool "Agilent AAEC-2000 based"
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select CPU_ARM920T
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select ARM_AMBA
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select HAVE_CLK
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help
This enables support for systems based on the Agilent AAEC-2000
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"
select ARM_AMBA
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select ARCH_HAS_CPUFREQ
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select HAVE_CLK
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select COMMON_CLKDEV
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select ICST525
help
Support for ARM's Integrator platform.
config ARCH_REALVIEW
bool "ARM Ltd. RealView family"
select ARM_AMBA
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select HAVE_CLK
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select COMMON_CLKDEV
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select ICST307
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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select ARCH_WANT_OPTIONAL_GPIOLIB
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help
This enables support for ARM Ltd RealView boards.
config ARCH_VERSATILE
bool "ARM Ltd. Versatile family"
select ARM_AMBA
select ARM_VIC
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select HAVE_CLK
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select COMMON_CLKDEV
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select ICST307
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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select ARCH_WANT_OPTIONAL_GPIOLIB
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help
This enables support for ARM Ltd Versatile board.
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config ARCH_AT91
bool "Atmel AT91"
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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select HAVE_CLK
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help
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This enables support for systems based on the Atmel AT91RM9200,
AT91SAM9 and AT91CAP9 processors.
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config ARCH_CLPS711X
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bool "Cirrus Logic CLPS711x/EP721x-based"
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select CPU_ARM720T
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help
Support for Cirrus Logic 711x/721x based boards.
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config ARCH_GEMINI
bool "Cortina Systems Gemini"
select CPU_FA526
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
help
Support for the Cortina Systems Gemini family SoCs
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config ARCH_EBSA110
bool "EBSA-110"
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select CPU_SA110
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select ISA
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select NO_IOPORT
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help
This is an evaluation board for the StrongARM processor available
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from Digital. It has limited hardware on-board, including an
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Ethernet interface, two PCMCIA sockets, two serial ports and a
parallel port.
[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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config ARCH_EP93XX
bool "EP93xx-based"
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select CPU_ARM920T
[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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select ARM_AMBA
select ARM_VIC
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select GENERIC_GPIO
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select HAVE_CLK
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select COMMON_CLKDEV
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_HAS_HOLES_MEMORYMODEL
[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-20 20:10:13 +03:00
help
This enables support for the Cirrus EP93xx series of CPUs.
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config ARCH_FOOTBRIDGE
bool "FootBridge"
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select CPU_SA110
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select FOOTBRIDGE
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help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
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config ARCH_MXC
bool "Freescale MXC/iMX-based"
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select ARCH_MTD_XIP
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
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select HAVE_CLK
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help
Support for Freescale MXC/iMX-based family of processors
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config ARCH_STMP3XXX
bool "Freescale STMP3xxx"
select CPU_ARM926T
select HAVE_CLK
select COMMON_CLKDEV
select ARCH_REQUIRE_GPIOLIB
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
select USB_ARCH_HAS_EHCI
help
Support for systems based on the Freescale 3xxx CPUs.
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config ARCH_NETX
bool "Hilscher NetX based"
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select CPU_ARM926T
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select ARM_VIC
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select GENERIC_CLOCKEVENTS
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select GENERIC_TIME
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help
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This enables support for systems based on the Hilscher NetX Soc
config ARCH_H720X
bool "Hynix HMS720x-based"
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select CPU_ARM720T
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select ISA_DMA_API
help
This enables support for systems based on the Hynix HMS720x
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config ARCH_NOMADIK
bool "STMicroelectronics Nomadik"
select ARM_AMBA
select ARM_VIC
select CPU_ARM926T
select HAVE_CLK
select COMMON_CLKDEV
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
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select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
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help
Support for the Nomadik platform by ST-Ericsson
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config ARCH_IOP13XX
bool "IOP13xx-based"
depends on MMU
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select CPU_XSC3
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select PLAT_IOP
select PCI
select ARCH_SUPPORTS_MSI
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select VMSPLIT_1G
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help
Support for Intel's IOP13XX (XScale) family of processors.
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config ARCH_IOP32X
bool "IOP32x-based"
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depends on MMU
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select CPU_XSCALE
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select PLAT_IOP
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select PCI
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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help
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Support for Intel's 80219 and IOP32X (XScale) family of
processors.
config ARCH_IOP33X
bool "IOP33x-based"
depends on MMU
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select CPU_XSCALE
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select PLAT_IOP
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select PCI
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
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help
Support for Intel's IOP33X (XScale) family of processors.
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config ARCH_IXP23XX
bool "IXP23XX-based"
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depends on MMU
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select CPU_XSC3
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select PCI
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help
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Support for Intel's IXP23xx (XScale) family of processors.
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config ARCH_IXP2000
bool "IXP2400/2800-based"
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depends on MMU
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select CPU_XSCALE
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select PCI
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help
Support for Intel's IXP2400/2800 (XScale) family of processors.
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config ARCH_IXP4XX
bool "IXP4xx-based"
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depends on MMU
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select CPU_XSCALE
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select GENERIC_GPIO
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select GENERIC_TIME
select GENERIC_CLOCKEVENTS
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select DMABOUNCE if PCI
[ARM] 3388/1: ixp23xx: add core ixp23xx support
Patch from Lennert Buytenhek
This patch adds support for the Intel ixp23xx series of CPUs. The
ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
Switch Fabric unit almost identical to the one on the ixp2400, two
xscale (8250ish) UARTs and a bunch of other stuff.
This patch adds the core ixp23xx support code, and support for the
ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
Espresso platforms.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-29 00:18:54 +04:00
help
2007-05-12 14:25:44 +04:00
Support for Intel's IXP4XX (XScale) family of processors.
[ARM] 3388/1: ixp23xx: add core ixp23xx support
Patch from Lennert Buytenhek
This patch adds support for the Intel ixp23xx series of CPUs. The
ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
Switch Fabric unit almost identical to the one on the ixp2400, two
xscale (8250ish) UARTs and a bunch of other stuff.
This patch adds the core ixp23xx support code, and support for the
ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
Espresso platforms.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-29 00:18:54 +04:00
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config ARCH_L7200
bool "LinkUp-L7200"
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select CPU_ARM720T
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select FIQ
help
Say Y here if you intend to run this kernel on a LinkUp Systems
L7200 Software Development Board which uses an ARM720T processor.
Information on this board can be obtained at:
<http://www.linkupsys.com/>
If you have any questions or comments about the Linux kernel port
to this board, send e-mail to <sjhill@cotw.com>.
[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:06 +04:00
config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
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select CPU_FEROCEON
[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:06 +04:00
select PCI
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select GENERIC_GPIO
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select ARCH_REQUIRE_GPIOLIB
[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:06 +04:00
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select PLAT_ORION
help
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:02 +04:00
config ARCH_LOKI
bool "Marvell Loki (88RC8480)"
2008-10-26 13:55:14 +03:00
select CPU_FEROCEON
[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:02 +04:00
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select PLAT_ORION
help
Support for the Marvell Loki (88RC8480) SoC.
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:10 +04:00
config ARCH_MV78XX0
bool "Marvell MV78xx0"
2008-10-26 13:55:14 +03:00
select CPU_FEROCEON
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:10 +04:00
select PCI
2008-10-20 03:51:04 +04:00
select GENERIC_GPIO
2009-05-29 04:08:55 +04:00
select ARCH_REQUIRE_GPIOLIB
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:10 +04:00
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select PLAT_ORION
help
Support for the following Marvell MV78xx0 series SoCs:
MV781x0, MV782x0.
2008-03-27 21:51:41 +03:00
config ARCH_ORION5X
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
bool "Marvell Orion"
depends on MMU
2008-10-26 13:55:14 +03:00
select CPU_FEROCEON
2007-10-23 23:14:42 +04:00
select PCI
2007-10-23 23:14:42 +04:00
select GENERIC_GPIO
2009-05-29 04:08:55 +04:00
select ARCH_REQUIRE_GPIOLIB
2007-10-23 23:14:42 +04:00
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
2008-03-27 21:51:39 +03:00
select PLAT_ORION
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
help
2008-03-27 21:51:41 +03:00
Support for the following Marvell Orion 5x series SoCs:
2008-05-31 10:30:40 +04:00
Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
[ARM] Orion: add 88F6183 (Orion-1-90) support
The Orion-1-90 (88F6183) is another member of the Orion SoC family,
which has a 16 bit DDR2 interface, one x1 PCIe port (configurable as
Root Complex or Endpoint), one 10/100/1000 ethernet interface, one
USB 2.0 port with PHY, one SPDIF/I2S interface, one SDIO interface,
one TWSI interface, two UARTs, one SPI interface, a NAND controller,
a crypto engine, and a 4-channel DMA engine.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-08-29 08:55:06 +04:00
Orion-2 (5281), Orion-1-90 (6183).
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
2009-04-26 17:21:59 +04:00
config ARCH_MMP
bool "Marvell PXA168/910"
depends on MMU
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
select COMMON_CLKDEV
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select TICK_ONESHOT
select PLAT_PXA
help
Support for Marvell's PXA168/910 processor line.
config ARCH_KS8695
bool "Micrel/Kendin KS8695"
select CPU_ARM922T
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
help
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
System-on-Chip devices.
config ARCH_NS9XXX
bool "NetSilicon NS9xxx"
select CPU_ARM926T
select GENERIC_GPIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select HAVE_CLK
help
Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
System.
<http://www.digi.com/products/microprocessors/index.jsp>
config ARCH_W90X900
bool "Nuvoton W90X900 CPU"
select CPU_ARM926T
2009-06-10 18:49:32 +04:00
select ARCH_REQUIRE_GPIOLIB
select GENERIC_GPIO
2009-07-14 18:09:54 +04:00
select HAVE_CLK
2009-06-10 18:50:44 +04:00
select COMMON_CLKDEV
2009-08-14 18:36:44 +04:00
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
2009-04-26 17:21:59 +04:00
help
2009-08-14 18:38:29 +04:00
Support for Nuvoton (Winbond logic dept.) ARM9 processor,
At present, the w90x900 has been renamed nuc900, regarding
the ARM series product line, you can login the following
link address to know more.
<http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
2009-04-26 17:21:59 +04:00
2006-06-21 00:30:44 +04:00
config ARCH_PNX4008
bool "Philips Nexperia PNX4008 Mobile"
2008-10-26 13:55:14 +03:00
select CPU_ARM926T
2008-07-24 08:26:48 +04:00
select HAVE_CLK
2006-06-21 00:30:44 +04:00
help
This enables support for Philips PNX4008 mobile platform.
2005-04-17 02:20:36 +04:00
config ARCH_PXA
2007-09-12 06:13:17 +04:00
bool "PXA2xx/PXA3xx-based"
2006-06-28 15:52:41 +04:00
depends on MMU
2005-12-20 00:27:59 +03:00
select ARCH_MTD_XIP
2009-07-31 02:23:24 +04:00
select ARCH_HAS_CPUFREQ
2007-03-05 11:30:18 +03:00
select GENERIC_GPIO
2008-07-24 08:26:48 +04:00
select HAVE_CLK
2008-11-08 23:25:21 +03:00
select COMMON_CLKDEV
2008-07-25 12:46:11 +04:00
select ARCH_REQUIRE_GPIOLIB
2007-02-06 00:37:07 +03:00
select GENERIC_TIME
2007-07-24 04:22:43 +04:00
select GENERIC_CLOCKEVENTS
2007-11-13 01:45:16 +03:00
select TICK_ONESHOT
2009-01-20 07:06:01 +03:00
select PLAT_PXA
2006-02-09 00:09:05 +03:00
help
2007-09-12 06:13:17 +04:00
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
2005-04-17 02:20:36 +04:00
2009-04-26 17:21:59 +04:00
config ARCH_MSM
bool "Qualcomm MSM"
select CPU_V6
2009-01-20 09:15:18 +03:00
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
help
2009-04-26 17:21:59 +04:00
Support for Qualcomm MSM7K based systems. This runs on the ARM11
apps processor of the MSM7K and depends on a shared memory
interface to the ARM9 modem processor which runs the baseband stack
and controls some vital subsystems (clock and power control, etc).
2009-01-20 09:15:18 +03:00
2005-04-17 02:20:36 +04:00
config ARCH_RPC
bool "RiscPC"
select ARCH_ACORN
select FIQ
select TIMER_ACORN
2005-09-06 04:48:42 +04:00
select ARCH_MAY_HAVE_PC_FDC
2008-07-01 17:16:49 +04:00
select HAVE_PATA_PLATFORM
2006-01-04 18:44:16 +03:00
select ISA_DMA_API
2007-02-11 18:41:31 +03:00
select NO_IOPORT
2008-10-01 20:11:06 +04:00
select ARCH_SPARSEMEM_ENABLE
2005-04-17 02:20:36 +04:00
help
On the Acorn Risc-PC, Linux can support the internal IDE disk and
CD-ROM interface, serial and parallel port, and the floppy drive.
config ARCH_SA1100
bool "SA1100-based"
2008-10-26 13:55:14 +03:00
select CPU_SA1100
2005-05-05 17:49:01 +04:00
select ISA
2006-11-30 23:43:51 +03:00
select ARCH_SPARSEMEM_ENABLE
2005-12-20 00:27:59 +03:00
select ARCH_MTD_XIP
2009-07-31 02:23:24 +04:00
select ARCH_HAS_CPUFREQ
2007-03-05 11:30:18 +03:00
select GENERIC_GPIO
2007-11-13 00:55:12 +03:00
select GENERIC_TIME
2008-04-15 02:03:10 +04:00
select GENERIC_CLOCKEVENTS
2008-07-24 08:26:48 +04:00
select HAVE_CLK
2008-04-15 02:03:10 +04:00
select TICK_ONESHOT
2008-07-25 12:46:11 +04:00
select ARCH_REQUIRE_GPIOLIB
2006-02-09 00:09:05 +03:00
help
Support for StrongARM 11x0 based boards.
2005-04-17 02:20:36 +04:00
config ARCH_S3C2410
2007-02-16 14:12:31 +03:00
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
2007-03-05 11:30:18 +03:00
select GENERIC_GPIO
2009-07-31 02:23:25 +04:00
select ARCH_HAS_CPUFREQ
2008-07-24 08:26:48 +04:00
select HAVE_CLK
2005-04-17 02:20:36 +04:00
help
Samsung S3C2410X CPU based systems, such as the Simtec Electronics
BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
2006-02-09 00:09:07 +03:00
the Samsung SMDK2410 development board (and derivatives).
2005-04-17 02:20:36 +04:00
2008-10-21 17:06:39 +04:00
config ARCH_S3C64XX
bool "Samsung S3C64XX"
select GENERIC_GPIO
select HAVE_CLK
2009-07-31 02:23:24 +04:00
select ARCH_HAS_CPUFREQ
2008-10-21 17:06:39 +04:00
help
Samsung S3C64XX series based systems
2009-06-23 16:39:42 +04:00
config ARCH_S5PC1XX
bool "Samsung S5PC1XX"
select GENERIC_GPIO
select HAVE_CLK
select CPU_V7
help
Samsung S5PC1XX series based systems
2005-04-17 02:20:36 +04:00
config ARCH_SHARK
bool "Shark"
2008-10-26 13:55:14 +03:00
select CPU_SA110
2005-05-05 17:49:01 +04:00
select ISA
select ISA_DMA
2008-10-07 23:14:55 +04:00
select ZONE_DMA
2005-05-05 17:49:01 +04:00
select PCI
2006-02-09 00:09:05 +03:00
help
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).
2005-04-17 02:20:36 +04:00
config ARCH_LH7A40X
bool "Sharp LH7A40X"
2008-10-26 13:55:14 +03:00
select CPU_ARM922T
2008-10-02 00:38:23 +04:00
select ARCH_DISCONTIGMEM_ENABLE if !LH7A40X_CONTIGMEM
select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
2005-04-17 02:20:36 +04:00
help
Say Y here for systems based on one of the Sharp LH7A40X
System on a Chip processors. These CPUs include an ARM922T
core with a wide array of integrated devices for
hand-held and low-power applications.
2009-04-27 13:21:46 +04:00
config ARCH_U300
bool "ST-Ericsson U300 Series"
depends on MMU
select CPU_ARM926T
2009-09-15 20:30:37 +04:00
select HAVE_TCM
2009-04-27 13:21:46 +04:00
select ARM_AMBA
select ARM_VIC
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select COMMON_CLKDEV
select GENERIC_GPIO
help
Support for ST-Ericsson U300 series mobile platforms.
2007-04-30 22:37:19 +04:00
config ARCH_DAVINCI
bool "TI DaVinci"
2008-10-26 13:55:14 +03:00
select CPU_ARM926T
2007-04-30 22:37:19 +04:00
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
2007-07-10 16:03:43 +04:00
select GENERIC_GPIO
2008-09-08 10:41:04 +04:00
select ARCH_REQUIRE_GPIOLIB
2008-07-24 08:26:48 +04:00
select HAVE_CLK
2008-10-07 23:14:55 +04:00
select ZONE_DMA
2009-04-09 01:49:38 +04:00
select HAVE_IDE
2009-03-21 03:29:01 +03:00
select COMMON_CLKDEV
2009-05-07 20:31:42 +04:00
select GENERIC_ALLOCATOR
2007-04-30 22:37:19 +04:00
help
Support for TI's DaVinci platform.
2007-05-12 14:25:44 +04:00
config ARCH_OMAP
bool "TI OMAP"
select GENERIC_GPIO
2008-07-24 08:26:48 +04:00
select HAVE_CLK
2008-07-25 12:46:11 +04:00
select ARCH_REQUIRE_GPIOLIB
2009-07-31 02:23:24 +04:00
select ARCH_HAS_CPUFREQ
2007-05-12 14:25:44 +04:00
select GENERIC_TIME
2007-10-19 10:04:43 +04:00
select GENERIC_CLOCKEVENTS
2007-05-12 14:25:44 +04:00
help
Support for TI's OMAP platform (OMAP1 and OMAP2).
2009-08-07 22:46:15 +04:00
config ARCH_BCMRING
bool "Broadcom BCMRING"
depends on MMU
select CPU_V6
select ARM_AMBA
select COMMON_CLKDEV
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
help
Support for Broadcom's BCMRing platform.
2005-04-17 02:20:36 +04:00
endchoice
source "arch/arm/mach-clps711x/Kconfig"
[ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek
This patch adds support for the Cirrus ep93xx series of CPUs. The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.
This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-20 20:10:13 +03:00
source "arch/arm/mach-ep93xx/Kconfig"
2005-04-17 02:20:36 +04:00
source "arch/arm/mach-footbridge/Kconfig"
2009-03-26 11:06:08 +03:00
source "arch/arm/mach-gemini/Kconfig"
2005-04-17 02:20:36 +04:00
source "arch/arm/mach-integrator/Kconfig"
2006-09-19 02:10:26 +04:00
source "arch/arm/mach-iop32x/Kconfig"
source "arch/arm/mach-iop33x/Kconfig"
2005-04-17 02:20:36 +04:00
2006-12-07 04:59:39 +03:00
source "arch/arm/mach-iop13xx/Kconfig"
2005-04-17 02:20:36 +04:00
source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-ixp2000/Kconfig"
[ARM] 3388/1: ixp23xx: add core ixp23xx support
Patch from Lennert Buytenhek
This patch adds support for the Intel ixp23xx series of CPUs. The
ixp23xx is an XSC3 based CPU with 512K of L2 cache, a 64bit 66MHz PCI
interface, two DDR RAM interfaces, QDR RAM interfaces, two gigabit
MACs, two 10/100 MACs, expansion bus, four microengines, a Media and
Switch Fabric unit almost identical to the one on the ixp2400, two
xscale (8250ish) UARTs and a bunch of other stuff.
This patch adds the core ixp23xx support code, and support for the
ADI Engineering Roadrunner, Intel IXDP2351, and IP Fabrics Double
Espresso platforms.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-29 00:18:54 +04:00
source "arch/arm/mach-ixp23xx/Kconfig"
[ARM] add Marvell Loki (88RC8480) SoC support
The Marvell Loki (88RC8480) is an ARM SoC based on a Feroceon CPU
core running at between 400 MHz and 1.0 GHz, and features a 64 bit
DDR controller, 512K of internal SRAM, two x4 PCI-Express ports,
two Gigabit Ethernet ports, two 4x SAS/SATA controllers, two UARTs,
two TWSI controllers, and IDMA/XOR engines.
This patch adds support for the Marvell LB88RC8480 Development
Board, enabling the use of the PCIe interfaces, the ethernet
interfaces, the TWSI interfaces and the UARTs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:02 +04:00
source "arch/arm/mach-loki/Kconfig"
[ARM] add Marvell 78xx0 ARM SoC support
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.
This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:10 +04:00
source "arch/arm/mach-mv78xx0/Kconfig"
2005-04-17 02:20:36 +04:00
source "arch/arm/mach-pxa/Kconfig"
2009-01-20 07:06:01 +03:00
source "arch/arm/plat-pxa/Kconfig"
2005-04-17 02:20:36 +04:00
2009-01-20 09:15:18 +03:00
source "arch/arm/mach-mmp/Kconfig"
2005-04-17 02:20:36 +04:00
source "arch/arm/mach-sa1100/Kconfig"
2005-07-10 22:58:17 +04:00
source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
2005-04-17 02:20:36 +04:00
2005-11-10 17:26:51 +03:00
source "arch/arm/mach-omap2/Kconfig"
2008-03-27 21:51:41 +03:00
source "arch/arm/mach-orion5x/Kconfig"
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
[ARM] add Marvell Kirkwood (88F6000) SoC support
The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.
This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
2008-06-23 00:45:06 +04:00
source "arch/arm/mach-kirkwood/Kconfig"
[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-23 23:14:41 +04:00
2007-02-11 20:31:01 +03:00
source "arch/arm/plat-s3c24xx/Kconfig"
2008-10-21 17:06:39 +04:00
source "arch/arm/plat-s3c64xx/Kconfig"
2007-07-22 19:07:09 +04:00
source "arch/arm/plat-s3c/Kconfig"
2009-06-23 16:39:42 +04:00
source "arch/arm/plat-s5pc1xx/Kconfig"
2007-02-11 20:31:01 +03:00
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
2005-04-17 02:20:36 +04:00
source "arch/arm/mach-s3c2410/Kconfig"
2007-02-11 20:31:01 +03:00
source "arch/arm/mach-s3c2412/Kconfig"
source "arch/arm/mach-s3c2440/Kconfig"
source "arch/arm/mach-s3c2442/Kconfig"
2007-02-16 14:12:31 +03:00
source "arch/arm/mach-s3c2443/Kconfig"
2007-02-11 20:31:01 +03:00
endif
2005-04-17 02:20:36 +04:00
2008-10-21 17:06:39 +04:00
if ARCH_S3C64XX
source "arch/arm/mach-s3c6400/Kconfig"
source "arch/arm/mach-s3c6410/Kconfig"
endif
2009-04-27 13:35:04 +04:00
source "arch/arm/plat-stmp3xxx/Kconfig"
2009-06-23 16:39:42 +04:00
if ARCH_S5PC1XX
source "arch/arm/mach-s5pc100/Kconfig"
endif
2005-04-17 02:20:36 +04:00
source "arch/arm/mach-lh7a40x/Kconfig"
source "arch/arm/mach-h720x/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
2005-06-20 21:51:05 +04:00
source "arch/arm/mach-aaec2000/Kconfig"
2005-10-31 17:25:02 +03:00
source "arch/arm/mach-realview/Kconfig"
2007-02-05 13:42:07 +03:00
source "arch/arm/mach-at91/Kconfig"
2006-01-09 20:05:41 +03:00
2007-07-10 01:06:53 +04:00
source "arch/arm/plat-mxc/Kconfig"
2009-07-02 22:06:47 +04:00
source "arch/arm/mach-nomadik/Kconfig"
2006-06-19 18:27:53 +04:00
source "arch/arm/mach-netx/Kconfig"
2007-02-16 17:36:55 +03:00
source "arch/arm/mach-ns9xxx/Kconfig"
2007-04-30 22:37:19 +04:00
source "arch/arm/mach-davinci/Kconfig"
2007-05-12 00:01:28 +04:00
source "arch/arm/mach-ks8695/Kconfig"
2007-11-26 15:12:13 +03:00
source "arch/arm/mach-msm/Kconfig"
2009-04-27 13:21:46 +04:00
source "arch/arm/mach-u300/Kconfig"
2008-12-03 05:55:38 +03:00
source "arch/arm/mach-w90x900/Kconfig"
2009-08-07 22:46:15 +04:00
source "arch/arm/mach-bcmring/Kconfig"
2005-04-17 02:20:36 +04:00
# Definitions to make life easier
config ARCH_ACORN
bool
2006-09-19 02:12:53 +04:00
config PLAT_IOP
bool
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config PLAT_ORION
bool
2009-01-20 07:06:01 +03:00
config PLAT_PXA
bool
2005-04-17 02:20:36 +04:00
source arch/arm/mm/Kconfig
[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)
Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch. Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.
CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.
This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.' This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.
These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 20:51:14 +03:00
config IWMMXT
bool "Enable iWMMXt support"
2009-02-26 04:34:35 +03:00
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
default y if PXA27x || PXA3xx || ARCH_MMP
[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)
Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch. Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.
CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.
This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.' This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.
These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 20:51:14 +03:00
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
2005-04-17 02:20:36 +04:00
# bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
config XSCALE_PMU
bool
depends on CPU_XSCALE && !XSCALE_PMU_TIMER
default y
2006-06-22 14:48:56 +04:00
if !MMU
source "arch/arm/Kconfig-nommu"
endif
2009-04-30 20:06:03 +04:00
config ARM_ERRATA_411920
bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
depends on CPU_V6 && !SMP
help
Invalidation of the Instruction Cache operation can
fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
It does not affect the MPCore. This option enables the ARM Ltd.
recommended workaround.
2009-04-30 20:06:09 +04:00
config ARM_ERRATA_430973
bool "ARM errata: Stale prediction on replaced interworking branch"
depends on CPU_V7
help
This option enables the workaround for the 430973 Cortex-A8
(r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
interworking branch is replaced with another code sequence at the
same virtual address, whether due to self-modifying code or virtual
to physical address re-mapping, Cortex-A8 does not recover from the
stale interworking branch prediction. This results in Cortex-A8
executing the new code sequence in the incorrect ARM or Thumb state.
The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
and also flushes the branch target cache at every context switch.
Note that setting specific bits in the ACTLR register may not be
available in non-secure mode.
2009-04-30 20:06:15 +04:00
config ARM_ERRATA_458693
bool "ARM errata: Processor deadlock when a false hazard is created"
depends on CPU_V7
help
This option enables the workaround for the 458693 Cortex-A8 (r2p0)
erratum. For very specific sequences of memory operations, it is
possible for a hazard condition intended for a cache line to instead
be incorrectly associated with a different cache line. This false
hazard might then cause a processor deadlock. The workaround enables
the L1 caching of the NEON accesses and disables the PLD instruction
in the ACTLR register. Note that setting specific bits in the ACTLR
register may not be available in non-secure mode.
2009-04-30 20:06:20 +04:00
config ARM_ERRATA_460075
bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
depends on CPU_V7
help
This option enables the workaround for the 460075 Cortex-A8 (r2p0)
erratum. Any asynchronous access to the L2 cache may encounter a
situation in which recent store transactions to the L2 cache are lost
and overwritten with stale memory contents from external memory. The
workaround disables the write-allocate mode for the L2 cache via the
ACTLR register. Note that setting specific bits in the ACTLR register
may not be available in non-secure mode.
2005-04-17 02:20:36 +04:00
endmenu
source "arch/arm/common/Kconfig"
config FORCE_MAX_ZONEORDER
int
depends on SA1111
default "9"
menu "Bus support"
config ARM_AMBA
bool
config ISA
bool
help
Find out whether you have ISA slots on your motherboard. ISA is the
name of a bus system, i.e. the way the CPU talks to the other stuff
inside your box. Other bus systems are PCI, EISA, MicroChannel
(MCA) or VESA. ISA is an older system, now being displaced by PCI;
newer boards don't support it. If you have ISA, say Y, otherwise N.
2006-01-04 18:44:16 +03:00
# Select ISA DMA controller support
2005-04-17 02:20:36 +04:00
config ISA_DMA
bool
2006-01-04 18:44:16 +03:00
select ISA_DMA_API
2005-04-17 02:20:36 +04:00
2006-01-04 18:44:16 +03:00
# Select ISA DMA interface
2005-05-04 08:39:22 +04:00
config ISA_DMA_API
bool
2005-04-17 02:20:36 +04:00
config PCI
2007-11-25 10:55:34 +03:00
bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
2005-04-17 02:20:36 +04:00
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
VESA. If you have PCI, say Y, otherwise N.
2007-07-10 20:54:40 +04:00
config PCI_SYSCALL
def_bool PCI
2005-04-17 02:20:36 +04:00
# Select the host bridge type
config PCI_HOST_VIA82C505
bool
depends on PCI && ARCH_SHARK
default y
2007-11-25 10:55:34 +03:00
config PCI_HOST_ITE8152
bool
depends on PCI && MACH_ARMCORE
default y
select DMABOUNCE
2005-04-17 02:20:36 +04:00
source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig"
endmenu
menu "Kernel Features"
2007-03-13 22:29:24 +03:00
source "kernel/time/Kconfig"
2005-04-17 02:20:36 +04:00
config SMP
bool "Symmetric Multi-Processing (EXPERIMENTAL)"
2009-06-11 18:35:00 +04:00
depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
2009-05-17 21:58:34 +04:00
depends on GENERIC_CLOCKEVENTS
2008-06-10 22:48:30 +04:00
select USE_GENERIC_SMP_HELPERS
2009-04-28 19:22:05 +04:00
select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
2005-04-17 02:20:36 +04:00
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
you have a system with more than one CPU, say Y.
If you say N here, the kernel will run on single and multiprocessor
machines, but will use only one CPU of a multiprocessor machine. If
you say Y here, the kernel will run on many, but not all, single
processor machines. On a single processor machine, the kernel will
run faster if you say N here.
2008-02-03 16:50:21 +03:00
See also <file:Documentation/i386/IO-APIC.txt>,
2005-04-17 02:20:36 +04:00
<file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
<http://www.linuxdoc.org/docs.html#howto>.
If you don't know what to do here, say N.
2009-05-16 14:51:14 +04:00
config HAVE_ARM_SCU
bool
depends on SMP
help
This option enables support for the ARM system coherency unit
2009-05-16 15:14:21 +04:00
config HAVE_ARM_TWD
bool
depends on SMP
help
This options enables support for the ARM timer and watchdog unit
2008-08-26 00:03:32 +04:00
choice
prompt "Memory split"
default VMSPLIT_3G
help
Select the desired split between kernel and user memory.
If you are not absolutely sure what you are doing, leave this
option alone!
config VMSPLIT_3G
bool "3G/1G user/kernel split"
config VMSPLIT_2G
bool "2G/2G user/kernel split"
config VMSPLIT_1G
bool "1G/3G user/kernel split"
endchoice
config PAGE_OFFSET
hex
default 0x40000000 if VMSPLIT_1G
default 0x80000000 if VMSPLIT_2G
default 0xC0000000
2005-04-17 02:20:36 +04:00
config NR_CPUS
int "Maximum number of CPUs (2-32)"
range 2 32
depends on SMP
default "4"
2005-11-03 01:24:33 +03:00
config HOTPLUG_CPU
bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
depends on SMP && HOTPLUG && EXPERIMENTAL
help
Say Y here to experiment with turning CPUs off and on. CPUs
can be controlled through /sys/devices/system/cpu.
2005-11-08 22:08:05 +03:00
config LOCAL_TIMERS
bool "Use local timer interrupts"
2009-06-11 18:35:00 +04:00
depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
2005-11-08 22:08:05 +03:00
default y
2009-04-28 19:22:05 +04:00
select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
2005-11-08 22:08:05 +03:00
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
accounting to be spread across the timer interval, preventing a
"thundering herd" at every timer tick.
2009-08-13 22:38:17 +04:00
source kernel/Kconfig.preempt
2005-04-17 02:20:36 +04:00
2006-03-03 01:41:59 +03:00
config HZ
int
default 128 if ARCH_L7200
default 200 if ARCH_EBSA110 || ARCH_S3C2410
2006-03-04 14:01:53 +03:00
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
2007-11-12 19:59:10 +03:00
default AT91_TIMER_HZ if ARCH_AT91
2006-03-03 01:41:59 +03:00
default 100
2009-07-24 15:33:02 +04:00
config THUMB2_KERNEL
bool "Compile the kernel in Thumb-2 mode"
depends on CPU_V7 && EXPERIMENTAL
select AEABI
select ARM_ASM_UNIFIED
help
By enabling this option, the kernel will be compiled in
Thumb-2 mode. A compiler/assembler that understand the unified
ARM-Thumb syntax is needed.
If unsure, say N.
2009-07-24 15:32:53 +04:00
config ARM_ASM_UNIFIED
bool
2006-01-14 19:33:50 +03:00
config AEABI
bool "Use the ARM EABI to compile the kernel"
help
This option allows for the kernel to be compiled using the latest
ARM ABI (aka EABI). This is only useful if you are using a user
space environment that is also compiled with EABI.
Since there are major incompatibilities between the legacy ABI and
EABI, especially with regard to structure member alignment, this
option also changes the kernel syscall calling convention to
disambiguate both ABIs and allow for backward compatibility support
(selected with CONFIG_OABI_COMPAT).
To use this you need GCC version 4.0.0 or later.
2006-01-14 19:37:15 +03:00
config OABI_COMPAT
2006-02-09 00:09:55 +03:00
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
2006-02-09 00:09:08 +03:00
depends on AEABI && EXPERIMENTAL
2006-01-14 19:37:15 +03:00
default y
help
This option preserves the old syscall interface along with the
new (ARM EABI) one. It also provides a compatibility layer to
intercept syscalls that have structure arguments which layout
in memory differs between the legacy ABI and the new ARM EABI
(only for non "thumb" binaries). This option adds a tiny
overhead to all syscalls and produces a slightly larger kernel.
If you know you'll be using only pure EABI user space then you
can say N here. If this option is not selected and you attempt
to execute a legacy ABI binary then the result will be
UNPREDICTABLE (in fact it can be predicted that it won't work
at all). If in doubt say Y.
2009-05-13 20:34:48 +04:00
config ARCH_HAS_HOLES_MEMORYMODEL
2008-08-14 14:10:14 +04:00
bool
2008-10-02 00:39:58 +04:00
# Discontigmem is deprecated
2005-06-23 11:07:43 +04:00
config ARCH_DISCONTIGMEM_ENABLE
2005-04-17 02:20:36 +04:00
bool
2006-11-30 23:43:51 +03:00
config ARCH_SPARSEMEM_ENABLE
bool
2008-10-02 00:39:58 +04:00
config ARCH_SPARSEMEM_DEFAULT
def_bool ARCH_SPARSEMEM_ENABLE
2006-11-30 23:43:51 +03:00
config ARCH_SELECT_MEMORY_MODEL
2008-10-02 00:39:58 +04:00
def_bool ARCH_DISCONTIGMEM_ENABLE && ARCH_SPARSEMEM_ENABLE
2006-11-30 23:43:51 +03:00
2006-04-11 09:53:53 +04:00
config NODES_SHIFT
int
default "4" if ARCH_LH7A40X
default "2"
depends on NEED_MULTIPLE_NODES
2008-09-19 08:36:12 +04:00
config HIGHMEM
bool "High Memory Support (EXPERIMENTAL)"
depends on MMU && EXPERIMENTAL
help
The address space of ARM processors is only 4 Gigabytes large
and it has to accommodate user address space, kernel address
space as well as some memory mapped IO. That means that, if you
have a large amount of physical memory and/or IO, not all of the
memory can be "permanently mapped" by the kernel. The physical
memory that is not permanently mapped is called "high memory".
Depending on the selected kernel/user memory split, minimum
vmalloc space and actual amount of RAM, you may not need this
option which should result in a slightly faster kernel.
If unsure, say n.
2009-08-17 23:02:06 +04:00
config HIGHPTE
bool "Allocate 2nd-level pagetables from highmem"
depends on HIGHMEM
depends on !OUTER_CACHE
2005-06-23 11:07:43 +04:00
source "mm/Kconfig"
2005-04-17 02:20:36 +04:00
config LEDS
bool "Timer and CPU usage LEDs"
2008-04-22 04:43:27 +04:00
depends on ARCH_CDB89712 || ARCH_EBSA110 || \
2009-04-01 14:40:15 +04:00
ARCH_EBSA285 || ARCH_INTEGRATOR || \
2005-04-17 02:20:36 +04:00
ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
2006-01-09 20:05:41 +03:00
ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
2008-09-17 00:36:30 +04:00
ARCH_AT91 || ARCH_DAVINCI || \
2009-05-30 16:56:13 +04:00
ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
2005-04-17 02:20:36 +04:00
help
If you say Y here, the LEDs on your machine will be used
to provide useful information about your current system status.
If you are compiling a kernel for a NetWinder or EBSA-285, you will
be able to select which LEDs are active using the options below. If
you are compiling a kernel for the EBSA-110 or the LART however, the
red LED will simply flash regularly to indicate that the system is
still functional. It is safe to say Y here if you have a CATS
system, but the driver will do nothing.
config LEDS_TIMER
bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
2007-04-02 23:48:10 +04:00
OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
|| MACH_OMAP_PERSEUS2
2005-04-17 02:20:36 +04:00
depends on LEDS
2007-03-13 22:29:24 +03:00
depends on !GENERIC_CLOCKEVENTS
2005-04-17 02:20:36 +04:00
default y if ARCH_EBSA110
help
If you say Y here, one of the system LEDs (the green one on the
NetWinder, the amber one on the EBSA285, or the red one on the LART)
will flash regularly to indicate that the system is still
operational. This is mainly useful to kernel hackers who are
debugging unstable kernels.
The LART uses the same LED for both Timer LED and CPU usage LED
functions. You may choose to use both, but the Timer LED function
will overrule the CPU usage LED.
config LEDS_CPU
bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
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!ARCH_OMAP) \
|| OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
|| MACH_OMAP_PERSEUS2
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depends on LEDS
help
If you say Y here, the red LED will be used to give a good real
time indication of CPU usage, by lighting whenever the idle task
is not currently executing.
The LART uses the same LED for both Timer LED and CPU usage LED
functions. You may choose to use both, but the Timer LED function
will overrule the CPU usage LED.
config ALIGNMENT_TRAP
bool
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depends on CPU_CP15_MMU
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default y if !ARCH_EBSA110
help
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ARM processors cannot fetch/store information which is not
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naturally aligned on the bus, i.e., a 4 byte fetch must start at an
address divisible by 4. On 32-bit ARM processors, these non-aligned
fetch/store instructions will be emulated in software if you say
here, which has a severe performance impact. This is necessary for
correct operation of some network protocols. With an IP-only
configuration it is safe to say N, otherwise say Y.
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config UACCESS_WITH_MEMCPY
bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
depends on MMU && EXPERIMENTAL
default y if CPU_FEROCEON
help
Implement faster copy_to_user and clear_user methods for CPU
cores where a 8-word STM instruction give significantly higher
memory write throughput than a sequence of individual 32bit stores.
A possible side effect is a slight increase in scheduling latency
between threads sharing the same address space if they invoke
such copy operations with large buffers.
However, if the CPU data cache is using a write-allocate mode,
this option is unlikely to provide any performance gain.
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endmenu
menu "Boot options"
# Compressed boot loader in ROM. Yes, we really want to ask about
# TEXT and BSS so we preserve their values in the config files.
config ZBOOT_ROM_TEXT
hex "Compressed ROM boot loader base address"
default "0"
help
The physical address at which the ROM-able zImage is to be
placed in the target. Platforms which normally make use of
ROM-able zImage formats normally set this to a suitable
value in their defconfig file.
If ZBOOT_ROM is not enabled, this has no effect.
config ZBOOT_ROM_BSS
hex "Compressed ROM boot loader BSS address"
default "0"
help
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The base address of an area of read/write memory in the target
for the ROM-able zImage which must be available while the
decompressor is running. It must be large enough to hold the
entire decompressed kernel plus an additional 128 KiB.
Platforms which normally make use of ROM-able zImage formats
normally set this to a suitable value in their defconfig file.
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If ZBOOT_ROM is not enabled, this has no effect.
config ZBOOT_ROM
bool "Compressed boot loader in ROM/flash"
depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
help
Say Y here if you intend to execute your compressed kernel image
(zImage) directly from ROM or flash. If unsure, say N.
config CMDLINE
string "Default kernel command string"
default ""
help
On some architectures (EBSA110 and CATS), there is currently no way
for the boot loader to pass arguments to the kernel. For these
architectures, you should supply some command-line options at build
time by entering them here. As a minimum, you should specify the
memory size and the root device (e.g., mem=64M root=/dev/nfs).
config XIP_KERNEL
bool "Kernel Execute-In-Place from ROM"
depends on !ZBOOT_ROM
help
Execute-In-Place allows the kernel to run from non-volatile storage
directly addressable by the CPU, such as NOR flash. This saves RAM
space since the text section of the kernel is not loaded from flash
to RAM. Read-write sections, such as the data section and stack,
are still copied to RAM. The XIP kernel is not compressed since
it has to run directly from flash, so it will take more space to
store it. The flash address used to link the kernel object files,
and for storing it, is configuration dependent. Therefore, if you
say Y here, you must know the proper physical address where to
store the kernel image depending on your own flash memory usage.
Also note that the make target becomes "make xipImage" rather than
"make zImage" or "make Image". The final kernel binary to put in
ROM memory will be arch/arm/boot/xipImage.
If unsure, say N.
config XIP_PHYS_ADDR
hex "XIP Kernel Physical Location"
depends on XIP_KERNEL
default "0x00080000"
help
This is the physical address in your flash memory the kernel will
be linked for and stored to. This address is dependent on your
own flash usage.
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config KEXEC
bool "Kexec system call (EXPERIMENTAL)"
depends on EXPERIMENTAL
help
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
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but it is independent of the system firmware. And like a reboot
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you can start any kernel with it, not just Linux.
It is an ongoing process to be certain the hardware in a machine
is properly shutdown, so do not be surprised if this code does not
initially work for you. It may help to enable device hotplugging
support.
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config ATAGS_PROC
bool "Export atags in procfs"
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depends on KEXEC
default y
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help
Should the atags used to boot the kernel be exported in an "atags"
file in procfs. Useful with kexec.
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endmenu
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menu "CPU Power Management"
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if ARCH_HAS_CPUFREQ
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source "drivers/cpufreq/Kconfig"
config CPU_FREQ_SA1100
bool
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depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
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default y
config CPU_FREQ_SA1110
bool
depends on CPU_FREQ && (SA1100_ASSABET || SA1100_CERF || SA1100_PT_SYSTEM3)
default y
config CPU_FREQ_INTEGRATOR
tristate "CPUfreq driver for ARM Integrator CPUs"
depends on ARCH_INTEGRATOR && CPU_FREQ
default y
help
This enables the CPUfreq driver for ARM Integrator CPUs.
For details, take a look at <file:Documentation/cpu-freq>.
If in doubt, say Y.
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config CPU_FREQ_PXA
bool
depends on CPU_FREQ && ARCH_PXA && PXA25x
default y
select CPU_FREQ_DEFAULT_GOV_USERSPACE
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config CPU_FREQ_S3C64XX
bool "CPUfreq support for Samsung S3C64XX CPUs"
depends on CPU_FREQ && CPU_S3C6410
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config CPU_FREQ_S3C
bool
help
Internal configuration node for common cpufreq on Samsung SoC
config CPU_FREQ_S3C24XX
bool "CPUfreq driver for Samsung S3C24XX series CPUs"
depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
select CPU_FREQ_S3C
help
This enables the CPUfreq driver for the Samsung S3C24XX family
of CPUs.
For details, take a look at <file:Documentation/cpu-freq>.
If in doubt, say N.
config CPU_FREQ_S3C24XX_PLL
bool "Support CPUfreq changing of PLL frequency"
depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
help
Compile in support for changing the PLL frequency from the
S3C24XX series CPUfreq driver. The PLL takes time to settle
after a frequency change, so by default it is not enabled.
This also means that the PLL tables for the selected CPU(s) will
be built which may increase the size of the kernel image.
config CPU_FREQ_S3C24XX_DEBUG
bool "Debug CPUfreq Samsung driver core"
depends on CPU_FREQ_S3C24XX
help
Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
config CPU_FREQ_S3C24XX_IODEBUG
bool "Debug CPUfreq Samsung driver IO timing"
depends on CPU_FREQ_S3C24XX
help
Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
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config CPU_FREQ_S3C24XX_DEBUGFS
bool "Export debugfs for CPUFreq"
depends on CPU_FREQ_S3C24XX && DEBUG_FS
help
Export status information via debugfs.
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endif
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source "drivers/cpuidle/Kconfig"
endmenu
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menu "Floating point emulation"
comment "At least one emulation must be selected"
config FPE_NWFPE
bool "NWFPE math emulation"
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depends on !AEABI || OABI_COMPAT
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---help---
Say Y to include the NWFPE floating point emulator in the kernel.
This is necessary to run most binaries. Linux does not currently
support floating point hardware so you need to say Y here even if
your machine has an FPA or floating point co-processor podule.
You may say N here if you are going to load the Acorn FPEmulator
early in the bootup.
config FPE_NWFPE_XP
bool "Support extended precision"
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depends on FPE_NWFPE
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help
Say Y to include 80-bit support in the kernel floating-point
emulator. Otherwise, only 32 and 64-bit support is compiled in.
Note that gcc does not generate 80-bit operations by default,
so in most cases this option only enlarges the size of the
floating point emulator without any good reason.
You almost surely want to say N here.
config FPE_FASTFPE
bool "FastFPE math emulation (EXPERIMENTAL)"
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depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
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---help---
Say Y here to include the FAST floating point emulator in the kernel.
This is an experimental much faster emulator which now also has full
precision for the mantissa. It does not support any exceptions.
It is very simple, and approximately 3-6 times faster than NWFPE.
It should be sufficient for most programs. It may be not suitable
for scientific calculations, but you have to check this for yourself.
If you do not feel you need a faster FP emulation you should better
choose NWFPE.
config VFP
bool "VFP-format floating point maths"
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depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
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help
Say Y to include VFP support code in the kernel. This is needed
if your hardware includes a VFP unit.
Please see <file:Documentation/arm/VFP/release-notes.txt> for
release notes and additional status information.
Say N if your target does not have VFP hardware.
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config VFPv3
bool
depends on VFP
default y if CPU_V7
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config NEON
bool "Advanced SIMD (NEON) Extension support"
depends on VFPv3 && CPU_V7
help
Say Y to include support code for NEON, the ARMv7 Advanced SIMD
Extension.
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endmenu
menu "Userspace binary formats"
source "fs/Kconfig.binfmt"
config ARTHUR
tristate "RISC OS personality"
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depends on !AEABI
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help
Say Y here to include the kernel code necessary if you want to run
Acorn RISC OS/Arthur binaries under Linux. This code is still very
experimental; if this sounds frightening, say N and sleep in peace.
You can also say M here to compile this support as a module (which
will be called arthur).
endmenu
menu "Power management options"
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source "kernel/power/Kconfig"
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config ARCH_SUSPEND_POSSIBLE
def_bool y
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endmenu
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source "net/Kconfig"
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source "drivers/Kconfig"
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source "fs/Kconfig"
source "arch/arm/Kconfig.debug"
source "security/Kconfig"
source "crypto/Kconfig"
source "lib/Kconfig"