License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 15:07:57 +01:00
/* SPDX-License-Identifier: GPL-2.0 */
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# ifndef _ASM_X86_MSR_INDEX_H
# define _ASM_X86_MSR_INDEX_H
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# include <linux/bits.h>
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/*
* CPU model specific register ( MSR ) numbers .
*
* Do not add new entries to this file unless the definitions are shared
* between multiple compilation units .
*/
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/* x86-64 specific MSRs */
# define MSR_EFER 0xc0000080 /* extended feature register */
# define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
# define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
# define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
# define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
# define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
# define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
# define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
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# define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
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/* EFER bits: */
# define _EFER_SCE 0 /* SYSCALL/SYSRET */
# define _EFER_LME 8 /* Long mode enable */
# define _EFER_LMA 10 /* Long mode active (read-only) */
# define _EFER_NX 11 /* No execute enable */
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# define _EFER_SVME 12 /* Enable virtualization */
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# define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
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# define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
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# define EFER_SCE (1<<_EFER_SCE)
# define EFER_LME (1<<_EFER_LME)
# define EFER_LMA (1<<_EFER_LMA)
# define EFER_NX (1<<_EFER_NX)
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# define EFER_SVME (1<<_EFER_SVME)
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# define EFER_LMSLE (1<<_EFER_LMSLE)
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# define EFER_FFXSR (1<<_EFER_FFXSR)
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/* Intel MSRs. Some also available on other CPUs */
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# define MSR_TEST_CTRL 0x00000033
# define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
# define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
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# define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
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# define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
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# define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
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# define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
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# define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
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# define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
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# define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
# define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
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# define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
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# define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
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# define MSR_PPIN_CTL 0x0000004e
# define MSR_PPIN 0x0000004f
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# define MSR_IA32_PERFCTR0 0x000000c1
# define MSR_IA32_PERFCTR1 0x000000c2
# define MSR_FSB_FREQ 0x000000cd
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# define MSR_PLATFORM_INFO 0x000000ce
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# define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
# define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
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# define MSR_IA32_UMWAIT_CONTROL 0xe1
# define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
# define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
/*
* The time field is bit [ 31 : 2 ] , but representing a 32 bit value with
* bit [ 1 : 0 ] zero .
*/
# define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
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/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
# define MSR_IA32_CORE_CAPS 0x000000cf
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# define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2
# define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
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# define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
# define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
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# define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
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# define NHM_C3_AUTO_DEMOTE (1UL << 25)
# define NHM_C1_AUTO_DEMOTE (1UL << 26)
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# define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
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# define SNB_C3_AUTO_UNDEMOTE (1UL << 27)
# define SNB_C1_AUTO_UNDEMOTE (1UL << 28)
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# define MSR_MTRRcap 0x000000fe
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# define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
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# define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
# define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
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# define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */
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# define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
# define ARCH_CAP_SSB_NO BIT(4) / *
* Not susceptible to Speculative Store Bypass
* attack , so no Speculative Store Bypass
* control required .
*/
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# define ARCH_CAP_MDS_NO BIT(5) / *
* Not susceptible to
* Microarchitectural Data
* Sampling ( MDS ) vulnerabilities .
*/
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# define ARCH_CAP_PSCHANGE_MC_NO BIT(6) / *
* The processor is not susceptible to a
* machine check error due to modifying the
* code page size along with either the
* physical address or cache type
* without TLB invalidation .
*/
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# define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
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# define ARCH_CAP_TAA_NO BIT(8) / *
* Not susceptible to
* TSX Async Abort ( TAA ) vulnerabilities .
*/
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# define ARCH_CAP_SBDR_SSDP_NO BIT(13) / *
* Not susceptible to SBDR and SSDP
* variants of Processor MMIO stale data
* vulnerabilities .
*/
# define ARCH_CAP_FBSDP_NO BIT(14) / *
* Not susceptible to FBSDP variant of
* Processor MMIO stale data
* vulnerabilities .
*/
# define ARCH_CAP_PSDP_NO BIT(15) / *
* Not susceptible to PSDP variant of
* Processor MMIO stale data
* vulnerabilities .
*/
# define ARCH_CAP_FB_CLEAR BIT(17) / *
* VERW clears CPU fill buffer
* even on MDS_NO CPUs .
*/
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# define ARCH_CAP_FB_CLEAR_CTRL BIT(18) / *
* MSR_IA32_MCU_OPT_CTRL [ FB_CLEAR_DIS ]
* bit available to control VERW
* behavior .
*/
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# define ARCH_CAP_RRSBA BIT(19) / *
* Indicates RET may use predictors
* other than the RSB . With eIBRS
* enabled predictions in kernel mode
* are restricted to targets in
* kernel .
*/
x86/speculation: Add RSB VM Exit protections
tl;dr: The Enhanced IBRS mitigation for Spectre v2 does not work as
documented for RET instructions after VM exits. Mitigate it with a new
one-entry RSB stuffing mechanism and a new LFENCE.
== Background ==
Indirect Branch Restricted Speculation (IBRS) was designed to help
mitigate Branch Target Injection and Speculative Store Bypass, i.e.
Spectre, attacks. IBRS prevents software run in less privileged modes
from affecting branch prediction in more privileged modes. IBRS requires
the MSR to be written on every privilege level change.
To overcome some of the performance issues of IBRS, Enhanced IBRS was
introduced. eIBRS is an "always on" IBRS, in other words, just turn
it on once instead of writing the MSR on every privilege level change.
When eIBRS is enabled, more privileged modes should be protected from
less privileged modes, including protecting VMMs from guests.
== Problem ==
Here's a simplification of how guests are run on Linux' KVM:
void run_kvm_guest(void)
{
// Prepare to run guest
VMRESUME();
// Clean up after guest runs
}
The execution flow for that would look something like this to the
processor:
1. Host-side: call run_kvm_guest()
2. Host-side: VMRESUME
3. Guest runs, does "CALL guest_function"
4. VM exit, host runs again
5. Host might make some "cleanup" function calls
6. Host-side: RET from run_kvm_guest()
Now, when back on the host, there are a couple of possible scenarios of
post-guest activity the host needs to do before executing host code:
* on pre-eIBRS hardware (legacy IBRS, or nothing at all), the RSB is not
touched and Linux has to do a 32-entry stuffing.
* on eIBRS hardware, VM exit with IBRS enabled, or restoring the host
IBRS=1 shortly after VM exit, has a documented side effect of flushing
the RSB except in this PBRSB situation where the software needs to stuff
the last RSB entry "by hand".
IOW, with eIBRS supported, host RET instructions should no longer be
influenced by guest behavior after the host retires a single CALL
instruction.
However, if the RET instructions are "unbalanced" with CALLs after a VM
exit as is the RET in #6, it might speculatively use the address for the
instruction after the CALL in #3 as an RSB prediction. This is a problem
since the (untrusted) guest controls this address.
Balanced CALL/RET instruction pairs such as in step #5 are not affected.
== Solution ==
The PBRSB issue affects a wide variety of Intel processors which
support eIBRS. But not all of them need mitigation. Today,
X86_FEATURE_RSB_VMEXIT triggers an RSB filling sequence that mitigates
PBRSB. Systems setting RSB_VMEXIT need no further mitigation - i.e.,
eIBRS systems which enable legacy IBRS explicitly.
However, such systems (X86_FEATURE_IBRS_ENHANCED) do not set RSB_VMEXIT
and most of them need a new mitigation.
Therefore, introduce a new feature flag X86_FEATURE_RSB_VMEXIT_LITE
which triggers a lighter-weight PBRSB mitigation versus RSB_VMEXIT.
The lighter-weight mitigation performs a CALL instruction which is
immediately followed by a speculative execution barrier (INT3). This
steers speculative execution to the barrier -- just like a retpoline
-- which ensures that speculation can never reach an unbalanced RET.
Then, ensure this CALL is retired before continuing execution with an
LFENCE.
In other words, the window of exposure is opened at VM exit where RET
behavior is troublesome. While the window is open, force RSB predictions
sampling for RET targets to a dead end at the INT3. Close the window
with the LFENCE.
There is a subset of eIBRS systems which are not vulnerable to PBRSB.
Add these systems to the cpu_vuln_whitelist[] as NO_EIBRS_PBRSB.
Future systems that aren't vulnerable will set ARCH_CAP_PBRSB_NO.
[ bp: Massage, incorporate review comments from Andy Cooper. ]
Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
Co-developed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
2022-08-02 15:47:01 -07:00
# define ARCH_CAP_PBRSB_NO BIT(24) / *
* Not susceptible to Post - Barrier
* Return Stack Buffer Predictions .
*/
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# define ARCH_CAP_XAPIC_DISABLE BIT(21) / *
* IA32_XAPIC_DISABLE_STATUS MSR
* supported
*/
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# define MSR_IA32_FLUSH_CMD 0x0000010b
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# define L1D_FLUSH BIT(0) / *
* Writeback and invalidate the
* L1 data cache .
*/
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# define MSR_IA32_BBL_CR_CTL 0x00000119
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# define MSR_IA32_BBL_CR_CTL3 0x0000011e
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# define MSR_IA32_TSX_CTRL 0x00000122
# define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
# define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
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# define MSR_IA32_MCU_OPT_CTRL 0x00000123
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# define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
# define RTM_ALLOW BIT(1) /* TSX development mode */
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# define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
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# define MSR_IA32_SYSENTER_CS 0x00000174
# define MSR_IA32_SYSENTER_ESP 0x00000175
# define MSR_IA32_SYSENTER_EIP 0x00000176
# define MSR_IA32_MCG_CAP 0x00000179
# define MSR_IA32_MCG_STATUS 0x0000017a
# define MSR_IA32_MCG_CTL 0x0000017b
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# define MSR_ERROR_CONTROL 0x0000017f
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# define MSR_IA32_MCG_EXT_CTL 0x000004d0
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# define MSR_OFFCORE_RSP_0 0x000001a6
# define MSR_OFFCORE_RSP_1 0x000001a7
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# define MSR_TURBO_RATIO_LIMIT 0x000001ad
# define MSR_TURBO_RATIO_LIMIT1 0x000001ae
# define MSR_TURBO_RATIO_LIMIT2 0x000001af
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# define MSR_LBR_SELECT 0x000001c8
# define MSR_LBR_TOS 0x000001c9
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# define MSR_IA32_POWER_CTL 0x000001fc
# define MSR_IA32_POWER_CTL_BIT_EE 19
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/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
# define MSR_INTEGRITY_CAPS 0x000002d9
# define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
# define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
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# define MSR_LBR_NHM_FROM 0x00000680
# define MSR_LBR_NHM_TO 0x000006c0
# define MSR_LBR_CORE_FROM 0x00000040
# define MSR_LBR_CORE_TO 0x00000060
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# define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
# define LBR_INFO_MISPRED BIT_ULL(63)
# define LBR_INFO_IN_TX BIT_ULL(62)
# define LBR_INFO_ABORT BIT_ULL(61)
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# define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
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# define LBR_INFO_CYCLES 0xffff
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# define LBR_INFO_BR_TYPE_OFFSET 56
# define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
# define MSR_ARCH_LBR_CTL 0x000014ce
# define ARCH_LBR_CTL_LBREN BIT(0)
# define ARCH_LBR_CTL_CPL_OFFSET 1
# define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
# define ARCH_LBR_CTL_STACK_OFFSET 3
# define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
# define ARCH_LBR_CTL_FILTER_OFFSET 16
# define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
# define MSR_ARCH_LBR_DEPTH 0x000014cf
# define MSR_ARCH_LBR_FROM_0 0x00001500
# define MSR_ARCH_LBR_TO_0 0x00001600
# define MSR_ARCH_LBR_INFO_0 0x00001200
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# define MSR_IA32_PEBS_ENABLE 0x000003f1
perf/x86/intel: Support adaptive PEBS v4
Adaptive PEBS is a new way to report PEBS sampling information. Instead
of a fixed size record for all PEBS events it allows to configure the
PEBS record to only include the information needed. Events can then opt
in to use such an extended record, or stay with a basic record which
only contains the IP.
The major new feature is to support LBRs in PEBS record.
Besides normal LBR, this allows (much faster) large PEBS, while still
supporting callstacks through callstack LBR. So essentially a lot of
profiling can now be done without frequent interrupts, dropping the
overhead significantly.
The main requirement still is to use a period, and not use frequency
mode, because frequency mode requires reevaluating the frequency on each
overflow.
The floating point state (XMM) is also supported, which allows efficient
profiling of FP function arguments.
Introduce specific drain function to handle variable length records.
Use a new callback to parse the new record format, and also handle the
STATUS field now being at a different offset.
Add code to set up the configuration register. Since there is only a
single register, all events either get the full super set of all events,
or only the basic record.
Originally-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: acme@kernel.org
Cc: jolsa@kernel.org
Link: https://lkml.kernel.org/r/20190402194509.2832-6-kan.liang@linux.intel.com
[ Renamed GPRS => GP. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-04-02 12:45:02 -07:00
# define MSR_PEBS_DATA_CFG 0x000003f2
2007-05-02 19:27:12 +02:00
# define MSR_IA32_DS_AREA 0x00000600
# define MSR_IA32_PERF_CAPABILITIES 0x00000345
perf/x86/intel: Hybrid PMU support for perf capabilities
Some platforms, e.g. Alder Lake, have hybrid architecture. Although most
PMU capabilities are the same, there are still some unique PMU
capabilities for different hybrid PMUs. Perf should register a dedicated
pmu for each hybrid PMU.
Add a new struct x86_hybrid_pmu, which saves the dedicated pmu and
capabilities for each hybrid PMU.
The architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicates the
architecture features which are available on all hybrid PMUs. The
architecture features are stored in the global x86_pmu.intel_cap.
For Alder Lake, the model-specific features are perf metrics and
PEBS-via-PT. The corresponding bits of the global x86_pmu.intel_cap
should be 0 for these two features. Perf should not use the global
intel_cap to check the features on a hybrid system.
Add a dedicated intel_cap in the x86_hybrid_pmu to store the
model-specific capabilities. Use the dedicated intel_cap to replace
the global intel_cap for thse two features. The dedicated intel_cap
will be set in the following "Add Alder Lake Hybrid support" patch.
Add is_hybrid() to distinguish a hybrid system. ADL may have an
alternative configuration. With that configuration, the
X86_FEATURE_HYBRID_CPU is not set. Perf cannot rely on the feature bit.
Add a new static_key_false, perf_is_hybrid, to indicate a hybrid system.
It will be assigned in the following "Add Alder Lake Hybrid support"
patch as well.
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1618237865-33448-5-git-send-email-kan.liang@linux.intel.com
2021-04-12 07:30:44 -07:00
# define PERF_CAP_METRICS_IDX 15
# define PERF_CAP_PT_IDX 16
2013-01-24 16:10:32 +01:00
# define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
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# define PERF_CAP_PEBS_TRAP BIT_ULL(6)
# define PERF_CAP_ARCH_REG BIT_ULL(7)
# define PERF_CAP_PEBS_FORMAT 0xf00
# define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
# define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE )
2007-05-02 19:27:12 +02:00
2015-01-30 12:39:52 +02:00
# define MSR_IA32_RTIT_CTL 0x00000570
2018-10-24 16:05:05 +08:00
# define RTIT_CTL_TRACEEN BIT(0)
# define RTIT_CTL_CYCLEACC BIT(1)
# define RTIT_CTL_OS BIT(2)
# define RTIT_CTL_USR BIT(3)
# define RTIT_CTL_PWR_EVT_EN BIT(4)
# define RTIT_CTL_FUP_ON_PTW BIT(5)
2018-10-24 16:05:08 +08:00
# define RTIT_CTL_FABRIC_EN BIT(6)
2018-10-24 16:05:05 +08:00
# define RTIT_CTL_CR3EN BIT(7)
# define RTIT_CTL_TOPA BIT(8)
# define RTIT_CTL_MTC_EN BIT(9)
# define RTIT_CTL_TSC_EN BIT(10)
# define RTIT_CTL_DISRETC BIT(11)
# define RTIT_CTL_PTW_EN BIT(12)
# define RTIT_CTL_BRANCH_EN BIT(13)
2022-01-26 12:48:14 +02:00
# define RTIT_CTL_EVENT_EN BIT(31)
2022-01-26 12:48:15 +02:00
# define RTIT_CTL_NOTNT BIT_ULL(55)
2018-10-24 16:05:05 +08:00
# define RTIT_CTL_MTC_RANGE_OFFSET 14
# define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
# define RTIT_CTL_CYC_THRESH_OFFSET 19
# define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
# define RTIT_CTL_PSB_FREQ_OFFSET 24
# define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
# define RTIT_CTL_ADDR0_OFFSET 32
# define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
# define RTIT_CTL_ADDR1_OFFSET 36
# define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
# define RTIT_CTL_ADDR2_OFFSET 40
# define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
# define RTIT_CTL_ADDR3_OFFSET 44
# define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
2015-01-30 12:39:52 +02:00
# define MSR_IA32_RTIT_STATUS 0x00000571
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# define RTIT_STATUS_FILTEREN BIT(0)
# define RTIT_STATUS_CONTEXTEN BIT(1)
# define RTIT_STATUS_TRIGGEREN BIT(2)
# define RTIT_STATUS_BUFFOVF BIT(3)
# define RTIT_STATUS_ERROR BIT(4)
# define RTIT_STATUS_STOPPED BIT(5)
2018-10-24 16:05:08 +08:00
# define RTIT_STATUS_BYTECNT_OFFSET 32
# define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
2016-04-27 18:44:44 +03:00
# define MSR_IA32_RTIT_ADDR0_A 0x00000580
# define MSR_IA32_RTIT_ADDR0_B 0x00000581
# define MSR_IA32_RTIT_ADDR1_A 0x00000582
# define MSR_IA32_RTIT_ADDR1_B 0x00000583
# define MSR_IA32_RTIT_ADDR2_A 0x00000584
# define MSR_IA32_RTIT_ADDR2_B 0x00000585
# define MSR_IA32_RTIT_ADDR3_A 0x00000586
# define MSR_IA32_RTIT_ADDR3_B 0x00000587
2015-01-30 12:39:52 +02:00
# define MSR_IA32_RTIT_CR3_MATCH 0x00000572
# define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
# define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
2007-05-02 19:27:12 +02:00
# define MSR_MTRRfix64K_00000 0x00000250
# define MSR_MTRRfix16K_80000 0x00000258
# define MSR_MTRRfix16K_A0000 0x00000259
# define MSR_MTRRfix4K_C0000 0x00000268
# define MSR_MTRRfix4K_C8000 0x00000269
# define MSR_MTRRfix4K_D0000 0x0000026a
# define MSR_MTRRfix4K_D8000 0x0000026b
# define MSR_MTRRfix4K_E0000 0x0000026c
# define MSR_MTRRfix4K_E8000 0x0000026d
# define MSR_MTRRfix4K_F0000 0x0000026e
# define MSR_MTRRfix4K_F8000 0x0000026f
# define MSR_MTRRdefType 0x000002ff
2008-03-18 17:00:14 -07:00
# define MSR_IA32_CR_PAT 0x00000277
2007-05-02 19:27:12 +02:00
# define MSR_IA32_DEBUGCTLMSR 0x000001d9
# define MSR_IA32_LASTBRANCHFROMIP 0x000001db
# define MSR_IA32_LASTBRANCHTOIP 0x000001dc
# define MSR_IA32_LASTINTFROMIP 0x000001dd
# define MSR_IA32_LASTINTTOIP 0x000001de
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# define MSR_IA32_PASID 0x00000d93
# define MSR_IA32_PASID_VALID BIT_ULL(31)
2008-01-30 13:30:54 +01:00
/* DEBUGCTLMSR bits (others vary by model): */
2010-03-25 14:51:49 +01:00
# define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
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# define DEBUGCTLMSR_BTF_SHIFT 1
2010-03-25 14:51:49 +01:00
# define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
2021-03-22 13:53:24 +00:00
# define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
2010-03-25 14:51:49 +01:00
# define DEBUGCTLMSR_TR (1UL << 6)
# define DEBUGCTLMSR_BTS (1UL << 7)
# define DEBUGCTLMSR_BTINT (1UL << 8)
# define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
# define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
# define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
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# define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12)
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# define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14
# define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
2008-01-30 13:30:54 +01:00
2015-09-09 14:53:59 -07:00
# define MSR_PEBS_FRONTEND 0x000003f7
2007-05-02 19:27:12 +02:00
# define MSR_IA32_MC0_CTL 0x00000400
# define MSR_IA32_MC0_STATUS 0x00000401
# define MSR_IA32_MC0_ADDR 0x00000402
# define MSR_IA32_MC0_MISC 0x00000403
2012-10-31 01:29:52 -04:00
/* C-state Residency Counters */
# define MSR_PKG_C3_RESIDENCY 0x000003f8
# define MSR_PKG_C6_RESIDENCY 0x000003f9
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# define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
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# define MSR_PKG_C7_RESIDENCY 0x000003fa
# define MSR_CORE_C3_RESIDENCY 0x000003fc
# define MSR_CORE_C6_RESIDENCY 0x000003fd
# define MSR_CORE_C7_RESIDENCY 0x000003fe
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# define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
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# define MSR_PKG_C2_RESIDENCY 0x0000060d
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# define MSR_PKG_C8_RESIDENCY 0x00000630
# define MSR_PKG_C9_RESIDENCY 0x00000631
# define MSR_PKG_C10_RESIDENCY 0x00000632
2012-10-31 01:29:52 -04:00
2016-04-06 17:15:55 -04:00
/* Interrupt Response Limit */
# define MSR_PKGC3_IRTL 0x0000060a
# define MSR_PKGC6_IRTL 0x0000060b
# define MSR_PKGC7_IRTL 0x0000060c
# define MSR_PKGC8_IRTL 0x00000633
# define MSR_PKGC9_IRTL 0x00000634
# define MSR_PKGC10_IRTL 0x00000635
2012-10-31 20:47:40 -04:00
/* Run Time Average Power Limiting (RAPL) Interface */
2021-08-20 17:42:43 +05:30
# define MSR_VR_CURRENT_CONFIG 0x00000601
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# define MSR_RAPL_POWER_UNIT 0x00000606
# define MSR_PKG_POWER_LIMIT 0x00000610
# define MSR_PKG_ENERGY_STATUS 0x00000611
# define MSR_PKG_PERF_STATUS 0x00000613
# define MSR_PKG_POWER_INFO 0x00000614
# define MSR_DRAM_POWER_LIMIT 0x00000618
# define MSR_DRAM_ENERGY_STATUS 0x00000619
# define MSR_DRAM_PERF_STATUS 0x0000061b
# define MSR_DRAM_POWER_INFO 0x0000061c
# define MSR_PP0_POWER_LIMIT 0x00000638
# define MSR_PP0_ENERGY_STATUS 0x00000639
# define MSR_PP0_POLICY 0x0000063a
# define MSR_PP0_PERF_STATUS 0x0000063b
# define MSR_PP1_POWER_LIMIT 0x00000640
# define MSR_PP1_ENERGY_STATUS 0x00000641
# define MSR_PP1_POLICY 0x00000642
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# define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
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# define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
2020-10-27 07:23:54 +00:00
# define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
2020-05-27 15:46:59 -07:00
2016-03-26 20:47:00 +02:00
/* Config TDP MSRs */
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# define MSR_CONFIG_TDP_NOMINAL 0x00000648
# define MSR_CONFIG_TDP_LEVEL_1 0x00000649
# define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
# define MSR_CONFIG_TDP_CONTROL 0x0000064B
# define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
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# define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
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# define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650
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2015-03-26 00:50:30 -04:00
# define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
# define MSR_PKG_ANY_CORE_C0_RES 0x00000659
# define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
# define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
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# define MSR_CORE_C1_RES 0x00000660
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# define MSR_MODULE_C6_RES_MS 0x00000664
2013-11-09 00:30:16 -05:00
2014-07-31 15:21:24 -04:00
# define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
# define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
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# define MSR_ATOM_CORE_RATIOS 0x0000066a
# define MSR_ATOM_CORE_VIDS 0x0000066b
# define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
# define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
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# define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
# define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
# define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
2022-03-08 16:30:35 +01:00
/* Control-flow Enforcement Technology MSRs */
# define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
# define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
# define CET_SHSTK_EN BIT_ULL(0)
# define CET_WRSS_EN BIT_ULL(1)
# define CET_ENDBR_EN BIT_ULL(2)
# define CET_LEG_IW_EN BIT_ULL(3)
# define CET_NO_TRACK_EN BIT_ULL(4)
# define CET_SUPPRESS_DISABLE BIT_ULL(5)
# define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
# define CET_SUPPRESS BIT_ULL(10)
# define CET_WAIT_ENDBR BIT_ULL(11)
# define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
# define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
# define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
# define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
# define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
2014-11-06 09:40:47 -08:00
/* Hardware P state interface */
# define MSR_PPERF 0x0000064e
# define MSR_PERF_LIMIT_REASONS 0x0000064f
# define MSR_PM_ENABLE 0x00000770
# define MSR_HWP_CAPABILITIES 0x00000771
# define MSR_HWP_REQUEST_PKG 0x00000772
# define MSR_HWP_INTERRUPT 0x00000773
# define MSR_HWP_REQUEST 0x00000774
# define MSR_HWP_STATUS 0x00000777
/* CPUID.6.EAX */
# define HWP_BASE_BIT (1<<7)
# define HWP_NOTIFICATIONS_BIT (1<<8)
# define HWP_ACTIVITY_WINDOW_BIT (1<<9)
# define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
# define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
/* IA32_HWP_CAPABILITIES */
2015-12-01 01:36:39 -05:00
# define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
# define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
# define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
# define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
2014-11-06 09:40:47 -08:00
/* IA32_HWP_REQUEST */
# define HWP_MIN_PERF(x) (x & 0xff)
# define HWP_MAX_PERF(x) ((x & 0xff) << 8)
# define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
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# define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
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# define HWP_EPP_PERFORMANCE 0x00
# define HWP_EPP_BALANCE_PERFORMANCE 0x80
# define HWP_EPP_BALANCE_POWERSAVE 0xC0
# define HWP_EPP_POWERSAVE 0xFF
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# define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
# define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
2014-11-06 09:40:47 -08:00
/* IA32_HWP_STATUS */
# define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
# define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
/* IA32_HWP_INTERRUPT */
# define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
# define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
2011-04-15 14:47:40 +02:00
# define MSR_AMD64_MC0_MASK 0xc0010044
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# define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
# define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
# define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
# define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
2011-04-15 14:47:40 +02:00
# define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
2009-02-12 13:49:35 +01:00
/* These are consecutive and not in the normal 4er MCE bank block */
# define MSR_IA32_MC0_CTL2 0x00000280
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# define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
2007-05-02 19:27:12 +02:00
# define MSR_P6_PERFCTR0 0x000000c1
# define MSR_P6_PERFCTR1 0x000000c2
# define MSR_P6_EVNTSEL0 0x00000186
# define MSR_P6_EVNTSEL1 0x00000187
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# define MSR_KNC_PERFCTR0 0x00000020
# define MSR_KNC_PERFCTR1 0x00000021
# define MSR_KNC_EVNTSEL0 0x00000028
# define MSR_KNC_EVNTSEL1 0x00000029
2013-06-25 08:12:33 -07:00
/* Alternative perfctr range with full access. */
# define MSR_IA32_PMC0 0x000004c1
perf/x86/intel: Support PEBS output to PT
If PEBS declares ability to output its data to Intel PT stream, use the
aux_output attribute bit to enable PEBS data output to PT. This requires
a PT event to be present and scheduled in the same context. Unlike the
DS area, the kernel does not extract PEBS records from the PT stream to
generate corresponding records in the perf stream, because that would
require real time in-kernel PT decoding, which is not feasible. The PMI,
however, can still be used.
The output setting is per-CPU, so all PEBS events must be either writing
to PT or to the DS area, therefore, in case of conflict, the conflicting
event will fail to schedule, allowing the rotation logic to alternate
between the PEBS->PT and PEBS->DS events.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: kan.liang@linux.intel.com
Link: https://lkml.kernel.org/r/20190806084606.4021-3-alexander.shishkin@linux.intel.com
2019-08-06 11:46:01 +03:00
/* Auto-reload via MSR instead of DS area */
# define MSR_RELOAD_PMC0 0x000014c1
# define MSR_RELOAD_FIXED_CTR0 0x00001309
2019-08-19 09:01:40 +02:00
/*
* AMD64 MSRs . Not complete . See the architecture manual for a more
* complete list .
*/
2008-12-16 19:16:34 +01:00
# define MSR_AMD64_PATCH_LEVEL 0x0000008b
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# define MSR_AMD64_TSC_RATIO 0xc0000104
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# define MSR_AMD64_NB_CFG 0xc001001f
2008-12-16 19:16:34 +01:00
# define MSR_AMD64_PATCH_LOADER 0xc0010020
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# define MSR_AMD_PERF_CTL 0xc0010062
# define MSR_AMD_PERF_STATUS 0xc0010063
# define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
2010-03-19 12:09:22 +01:00
# define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
# define MSR_AMD64_OSVW_STATUS 0xc0010141
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# define MSR_AMD_PPIN_CTL 0xc00102f0
# define MSR_AMD_PPIN 0xc00102f1
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# define MSR_AMD64_CPUID_FN_1 0xc0011004
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# define MSR_AMD64_LS_CFG 0xc0011020
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# define MSR_AMD64_DC_CFG 0xc0011022
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# define MSR_AMD64_BU_CFG2 0xc001102a
2007-10-19 20:35:03 +02:00
# define MSR_AMD64_IBSFETCHCTL 0xc0011030
# define MSR_AMD64_IBSFETCHLINAD 0xc0011031
# define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
2011-12-15 17:56:37 +01:00
# define MSR_AMD64_IBSFETCH_REG_COUNT 3
# define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
2007-10-19 20:35:03 +02:00
# define MSR_AMD64_IBSOPCTL 0xc0011033
# define MSR_AMD64_IBSOPRIP 0xc0011034
# define MSR_AMD64_IBSOPDATA 0xc0011035
# define MSR_AMD64_IBSOPDATA2 0xc0011036
# define MSR_AMD64_IBSOPDATA3 0xc0011037
# define MSR_AMD64_IBSDCLINAD 0xc0011038
# define MSR_AMD64_IBSDCPHYSAD 0xc0011039
2011-12-15 17:56:37 +01:00
# define MSR_AMD64_IBSOP_REG_COUNT 7
# define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
2007-10-19 20:35:03 +02:00
# define MSR_AMD64_IBSCTL 0xc001103a
2010-09-21 15:49:31 +02:00
# define MSR_AMD64_IBSBRTARGET 0xc001103b
2020-09-08 16:47:38 -05:00
# define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
2014-11-10 14:24:26 -06:00
# define MSR_AMD64_IBSOPDATA4 0xc001103d
2011-12-15 17:56:37 +01:00
# define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
2022-02-07 17:54:26 +02:00
# define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
2020-12-10 11:09:36 -06:00
# define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
2020-09-07 15:15:20 +02:00
# define MSR_AMD64_SEV_ES_GHCB 0xc0010130
2017-10-20 09:30:54 -05:00
# define MSR_AMD64_SEV 0xc0010131
# define MSR_AMD64_SEV_ENABLED_BIT 0
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# define MSR_AMD64_SEV_ES_ENABLED_BIT 1
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# define MSR_AMD64_SEV_SNP_ENABLED_BIT 2
2017-10-20 09:30:54 -05:00
# define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
2020-09-07 15:15:37 +02:00
# define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
2022-02-24 10:55:49 -06:00
# define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
2007-10-19 20:35:03 +02:00
2018-05-17 17:09:18 +02:00
# define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
2021-12-24 09:04:56 +08:00
/* AMD Collaborative Processor Performance Control MSRs */
# define MSR_AMD_CPPC_CAP1 0xc00102b0
# define MSR_AMD_CPPC_ENABLE 0xc00102b1
# define MSR_AMD_CPPC_CAP2 0xc00102b2
# define MSR_AMD_CPPC_REQ 0xc00102b3
# define MSR_AMD_CPPC_STATUS 0xc00102b4
# define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
# define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
# define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
# define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
# define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
# define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
# define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
# define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
2022-04-21 11:16:54 +05:30
/* AMD Performance Counter Global Status and Control MSRs */
# define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
# define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
# define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
2022-08-11 17:59:54 +05:30
/* AMD Last Branch Record MSRs */
# define MSR_AMD64_LBR_SELECT 0xc000010e
2016-01-29 16:29:57 +08:00
/* Fam 17h MSRs */
# define MSR_F17H_IRPERF 0xc00000e9
2022-06-14 23:16:04 +02:00
# define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
# define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
2013-04-19 16:34:28 -05:00
/* Fam 16h MSRs */
# define MSR_F16H_L2I_PERF_CTL 0xc0010230
# define MSR_F16H_L2I_PERF_CTR 0xc0010231
2014-05-29 17:26:50 +02:00
# define MSR_F16H_DR1_ADDR_MASK 0xc0011019
# define MSR_F16H_DR2_ADDR_MASK 0xc001101a
# define MSR_F16H_DR3_ADDR_MASK 0xc001101b
# define MSR_F16H_DR0_ADDR_MASK 0xc0011027
2013-04-19 16:34:28 -05:00
2010-09-24 15:54:43 +02:00
/* Fam 15h MSRs */
2020-06-21 12:41:53 +02:00
# define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
# define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
2010-09-24 15:54:43 +02:00
# define MSR_F15H_PERF_CTL 0xc0010200
2018-02-05 13:24:51 -06:00
# define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
# define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
# define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
# define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
# define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
# define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
2010-09-24 15:54:43 +02:00
# define MSR_F15H_PERF_CTR 0xc0010201
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# define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
# define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
# define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
# define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
# define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
# define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
2013-02-06 11:26:29 -06:00
# define MSR_F15H_NB_PERF_CTL 0xc0010240
# define MSR_F15H_NB_PERF_CTR 0xc0010241
2016-01-29 16:29:56 +08:00
# define MSR_F15H_PTSC 0xc0010280
2015-11-23 11:12:23 +01:00
# define MSR_F15H_IC_CFG 0xc0011021
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# define MSR_F15H_EX_CFG 0xc001102c
2010-09-24 15:54:43 +02:00
2008-01-30 13:33:18 +01:00
/* Fam 10h MSRs */
# define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
# define FAM10H_MMIO_CONF_ENABLE (1<<0)
# define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
# define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
2010-11-16 08:25:08 +00:00
# define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
2008-01-30 13:33:18 +01:00
# define FAM10H_MMIO_CONF_BASE_SHIFT 20
2009-12-16 15:43:55 +01:00
# define MSR_FAM10H_NODE_ID 0xc001100c
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# define MSR_F10H_DECFG 0xc0011029
# define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
2018-01-08 16:09:32 -06:00
# define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
2008-01-30 13:33:18 +01:00
2007-10-19 20:35:03 +02:00
/* K8 MSRs */
# define MSR_K8_TOP_MEM1 0xc001001a
# define MSR_K8_TOP_MEM2 0xc001001d
2021-04-27 06:16:36 -05:00
# define MSR_AMD64_SYSCFG 0xc0010010
# define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
# define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
2008-06-09 17:11:13 +02:00
# define MSR_K8_INT_PENDING_MSG 0xc0010055
/* C1E active bits in int pending message */
# define K8_INTP_C1E_ACTIVE_MASK 0x18000000
2008-03-12 03:53:32 +01:00
# define MSR_K8_TSEG_ADDR 0xc0010112
2015-09-18 17:33:04 +02:00
# define MSR_K8_TSEG_MASK 0xc0010113
2007-10-19 20:35:03 +02:00
# define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
# define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
# define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
/* K7 MSRs */
2007-05-02 19:27:12 +02:00
# define MSR_K7_EVNTSEL0 0xc0010000
# define MSR_K7_PERFCTR0 0xc0010004
# define MSR_K7_EVNTSEL1 0xc0010001
# define MSR_K7_PERFCTR1 0xc0010005
# define MSR_K7_EVNTSEL2 0xc0010002
# define MSR_K7_PERFCTR2 0xc0010006
# define MSR_K7_EVNTSEL3 0xc0010003
# define MSR_K7_PERFCTR3 0xc0010007
# define MSR_K7_CLK_CTL 0xc001001b
# define MSR_K7_HWCR 0xc0010015
2017-12-04 10:57:23 -06:00
# define MSR_K7_HWCR_SMMLOCK_BIT 0
# define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
2020-02-19 18:52:43 +01:00
# define MSR_K7_HWCR_IRPERF_EN_BIT 30
# define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
2007-05-02 19:27:12 +02:00
# define MSR_K7_FID_VID_CTL 0xc0010041
# define MSR_K7_FID_VID_STATUS 0xc0010042
/* K6 MSRs */
# define MSR_K6_WHCR 0xc0000082
# define MSR_K6_UWCCR 0xc0000085
# define MSR_K6_EPMR 0xc0000086
# define MSR_K6_PSOR 0xc0000087
# define MSR_K6_PFIR 0xc0000088
/* Centaur-Hauls/IDT defined MSRs. */
# define MSR_IDT_FCR1 0x00000107
# define MSR_IDT_FCR2 0x00000108
# define MSR_IDT_FCR3 0x00000109
# define MSR_IDT_FCR4 0x0000010a
# define MSR_IDT_MCR0 0x00000110
# define MSR_IDT_MCR1 0x00000111
# define MSR_IDT_MCR2 0x00000112
# define MSR_IDT_MCR3 0x00000113
# define MSR_IDT_MCR4 0x00000114
# define MSR_IDT_MCR5 0x00000115
# define MSR_IDT_MCR6 0x00000116
# define MSR_IDT_MCR7 0x00000117
# define MSR_IDT_MCR_CTRL 0x00000120
/* VIA Cyrix defined MSRs*/
# define MSR_VIA_FCR 0x00001107
# define MSR_VIA_LONGHAUL 0x0000110a
# define MSR_VIA_RNG 0x0000110b
# define MSR_VIA_BCR2 0x00001147
/* Transmeta defined MSRs */
# define MSR_TMTA_LONGRUN_CTRL 0x80868010
# define MSR_TMTA_LONGRUN_FLAGS 0x80868011
# define MSR_TMTA_LRTI_READOUT 0x80868018
# define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
/* Intel defined MSRs. */
# define MSR_IA32_P5_MC_ADDR 0x00000000
# define MSR_IA32_P5_MC_TYPE 0x00000001
# define MSR_IA32_TSC 0x00000010
# define MSR_IA32_PLATFORM_ID 0x00000017
# define MSR_IA32_EBL_CR_POWERON 0x0000002a
2010-09-09 12:06:45 +02:00
# define MSR_EBC_FREQUENCY_ID 0x0000002c
2013-02-10 17:19:24 -05:00
# define MSR_SMI_COUNT 0x00000034
x86/msr-index: Clean up bit defines for IA32_FEATURE_CONTROL MSR
As pointed out by Boris, the defines for bits in IA32_FEATURE_CONTROL
are quite a mouthful, especially the VMX bits which must differentiate
between enabling VMX inside and outside SMX (TXT) operation. Rename the
MSR and its bit defines to abbreviate FEATURE_CONTROL as FEAT_CTL to
make them a little friendlier on the eyes.
Arguably, the MSR itself should keep the full IA32_FEATURE_CONTROL name
to match Intel's SDM, but a future patch will add a dedicated Kconfig,
file and functions for the MSR. Using the full name for those assets is
rather unwieldy, so bite the bullet and use IA32_FEAT_CTL so that its
nomenclature is consistent throughout the kernel.
Opportunistically, fix a few other annoyances with the defines:
- Relocate the bit defines so that they immediately follow the MSR
define, e.g. aren't mistaken as belonging to MISC_FEATURE_CONTROL.
- Add whitespace around the block of feature control defines to make
it clear they're all related.
- Use BIT() instead of manually encoding the bit shift.
- Use "VMX" instead of "VMXON" to match the SDM.
- Append "_ENABLED" to the LMCE (Local Machine Check Exception) bit to
be consistent with the kernel's verbiage used for all other feature
control bits. Note, the SDM refers to the LMCE bit as LMCE_ON,
likely to differentiate it from IA32_MCG_EXT_CTL.LMCE_EN. Ignore
the (literal) one-off usage of _ON, the SDM is simply "wrong".
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20191221044513.21680-2-sean.j.christopherson@intel.com
2019-12-20 20:44:55 -08:00
/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
# define MSR_IA32_FEAT_CTL 0x0000003a
# define FEAT_CTL_LOCKED BIT(0)
# define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1)
# define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2)
x86/{cpufeatures,msr}: Add Intel SGX Launch Control hardware bits
The SGX Launch Control hardware helps restrict which enclaves the
hardware will run. Launch control is intended to restrict what software
can run with enclave protections, which helps protect the overall system
from bad enclaves.
For the kernel's purposes, there are effectively two modes in which the
launch control hardware can operate: rigid and flexible. In its rigid
mode, an entity other than the kernel has ultimate authority over which
enclaves can be run (firmware, Intel, etc...). In its flexible mode, the
kernel has ultimate authority over which enclaves can run.
Enable X86_FEATURE_SGX_LC to enumerate when the CPU supports SGX Launch
Control in general.
Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a
SHA256 hash of a 3072-bit RSA public key. The hardware allows SGX enclaves
signed with this public key to initialize and run [*]. Enclaves not signed
with this key can not initialize and run.
Add FEAT_CTL_SGX_LC_ENABLED, which informs whether the SGXLEPUBKEYHASH MSRs
can be written by the kernel.
If the MSRs do not exist or are read-only, the launch control hardware is
operating in rigid mode. Linux does not and will not support creating
enclaves when hardware is configured in rigid mode because it takes away
the authority for launch decisions from the kernel. Note, this does not
preclude KVM from virtualizing/exposing SGX to a KVM guest when launch
control hardware is operating in rigid mode.
[*] Intel SDM: 38.1.4 Intel SGX Launch Control Configuration
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Co-developed-by: Jarkko Sakkinen <jarkko@kernel.org>
Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Jethro Beekman <jethro@fortanix.com>
Link: https://lkml.kernel.org/r/20201112220135.165028-5-jarkko@kernel.org
2020-11-13 00:01:15 +02:00
# define FEAT_CTL_SGX_LC_ENABLED BIT(17)
2020-11-13 00:01:14 +02:00
# define FEAT_CTL_SGX_ENABLED BIT(18)
x86/msr-index: Clean up bit defines for IA32_FEATURE_CONTROL MSR
As pointed out by Boris, the defines for bits in IA32_FEATURE_CONTROL
are quite a mouthful, especially the VMX bits which must differentiate
between enabling VMX inside and outside SMX (TXT) operation. Rename the
MSR and its bit defines to abbreviate FEATURE_CONTROL as FEAT_CTL to
make them a little friendlier on the eyes.
Arguably, the MSR itself should keep the full IA32_FEATURE_CONTROL name
to match Intel's SDM, but a future patch will add a dedicated Kconfig,
file and functions for the MSR. Using the full name for those assets is
rather unwieldy, so bite the bullet and use IA32_FEAT_CTL so that its
nomenclature is consistent throughout the kernel.
Opportunistically, fix a few other annoyances with the defines:
- Relocate the bit defines so that they immediately follow the MSR
define, e.g. aren't mistaken as belonging to MISC_FEATURE_CONTROL.
- Add whitespace around the block of feature control defines to make
it clear they're all related.
- Use BIT() instead of manually encoding the bit shift.
- Use "VMX" instead of "VMXON" to match the SDM.
- Append "_ENABLED" to the LMCE (Local Machine Check Exception) bit to
be consistent with the kernel's verbiage used for all other feature
control bits. Note, the SDM refers to the LMCE bit as LMCE_ON,
likely to differentiate it from IA32_MCG_EXT_CTL.LMCE_EN. Ignore
the (literal) one-off usage of _ON, the SDM is simply "wrong".
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20191221044513.21680-2-sean.j.christopherson@intel.com
2019-12-20 20:44:55 -08:00
# define FEAT_CTL_LMCE_ENABLED BIT(20)
2012-11-29 12:42:50 -08:00
# define MSR_IA32_TSC_ADJUST 0x0000003b
2014-02-24 10:55:46 +00:00
# define MSR_IA32_BNDCFGS 0x00000d90
2007-05-02 19:27:12 +02:00
2017-05-23 11:52:54 -07:00
# define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
2021-10-21 15:55:17 -07:00
# define MSR_IA32_XFD 0x000001c4
# define MSR_IA32_XFD_ERR 0x000001c5
2014-05-29 11:12:30 -07:00
# define MSR_IA32_XSS 0x00000da0
2007-05-02 19:27:12 +02:00
# define MSR_IA32_APICBASE 0x0000001b
# define MSR_IA32_APICBASE_BSP (1<<8)
# define MSR_IA32_APICBASE_ENABLE (1<<11)
# define MSR_IA32_APICBASE_BASE (0xfffff<<12)
# define MSR_IA32_UCODE_WRITE 0x00000079
# define MSR_IA32_UCODE_REV 0x0000008b
x86/{cpufeatures,msr}: Add Intel SGX Launch Control hardware bits
The SGX Launch Control hardware helps restrict which enclaves the
hardware will run. Launch control is intended to restrict what software
can run with enclave protections, which helps protect the overall system
from bad enclaves.
For the kernel's purposes, there are effectively two modes in which the
launch control hardware can operate: rigid and flexible. In its rigid
mode, an entity other than the kernel has ultimate authority over which
enclaves can be run (firmware, Intel, etc...). In its flexible mode, the
kernel has ultimate authority over which enclaves can run.
Enable X86_FEATURE_SGX_LC to enumerate when the CPU supports SGX Launch
Control in general.
Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a
SHA256 hash of a 3072-bit RSA public key. The hardware allows SGX enclaves
signed with this public key to initialize and run [*]. Enclaves not signed
with this key can not initialize and run.
Add FEAT_CTL_SGX_LC_ENABLED, which informs whether the SGXLEPUBKEYHASH MSRs
can be written by the kernel.
If the MSRs do not exist or are read-only, the launch control hardware is
operating in rigid mode. Linux does not and will not support creating
enclaves when hardware is configured in rigid mode because it takes away
the authority for launch decisions from the kernel. Note, this does not
preclude KVM from virtualizing/exposing SGX to a KVM guest when launch
control hardware is operating in rigid mode.
[*] Intel SDM: 38.1.4 Intel SGX Launch Control Configuration
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Co-developed-by: Jarkko Sakkinen <jarkko@kernel.org>
Signed-off-by: Jarkko Sakkinen <jarkko@kernel.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Jethro Beekman <jethro@fortanix.com>
Link: https://lkml.kernel.org/r/20201112220135.165028-5-jarkko@kernel.org
2020-11-13 00:01:15 +02:00
/* Intel SGX Launch Enclave Public Key Hash MSRs */
# define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
# define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
# define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
# define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
2014-12-11 08:53:27 +03:00
# define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
# define MSR_IA32_SMBASE 0x0000009e
2007-05-02 19:27:12 +02:00
# define MSR_IA32_PERF_STATUS 0x00000198
# define MSR_IA32_PERF_CTL 0x00000199
2014-12-19 23:13:51 +05:30
# define INTEL_PERF_CTL_MASK 0xffff
2007-05-02 19:27:12 +02:00
perf/x86/amd: Add AMD Fam19h Branch Sampling support
Add support for the AMD Fam19h 16-deep branch sampling feature as
described in the AMD PPR Fam19h Model 01h Revision B1. This is a model
specific extension. It is not an architected AMD feature.
The Branch Sampling (BRS) operates with a 16-deep saturating buffer in MSR
registers. There is no branch type filtering. All control flow changes are
captured. BRS relies on specific programming of the core PMU of Fam19h. In
particular, the following requirements must be met:
- the sampling period be greater than 16 (BRS depth)
- the sampling period must use a fixed and not frequency mode
BRS interacts with the NMI interrupt as well. Because enabling BRS is
expensive, it is only activated after P event occurrences, where P is the
desired sampling period. At P occurrences of the event, the counter
overflows, the CPU catches the interrupt, activates BRS for 16 branches until
it saturates, and then delivers the NMI to the kernel. Between the overflow
and the time BRS activates more branches may be executed skewing the period.
All along, the sampling event keeps counting. The skid may be attenuated by
reducing the sampling period by 16 (subsequent patch).
BRS is integrated into perf_events seamlessly via the same
PERF_RECORD_BRANCH_STACK sample format. BRS generates perf_branch_entry
records in the sampling buffer. No prediction information is supported. The
branches are stored in reverse order of execution. The most recent branch is
the first entry in each record.
No modification to the perf tool is necessary.
BRS can be used with any sampling event. However, it is recommended to use
the RETIRED_BRANCH_INSTRUCTIONS event because it matches what the BRS
captures.
$ perf record -b -c 1000037 -e cpu/event=0xc2,name=ret_br_instructions/ test
$ perf report -D
56531696056126 0x193c000 [0x1a8]: PERF_RECORD_SAMPLE(IP, 0x2): 18122/18230: 0x401d24 period: 1000037 addr: 0
... branch stack: nr:16
..... 0: 0000000000401d24 -> 0000000000401d5a 0 cycles 0
..... 1: 0000000000401d5c -> 0000000000401d24 0 cycles 0
..... 2: 0000000000401d22 -> 0000000000401d5c 0 cycles 0
..... 3: 0000000000401d5e -> 0000000000401d22 0 cycles 0
..... 4: 0000000000401d20 -> 0000000000401d5e 0 cycles 0
..... 5: 0000000000401d3e -> 0000000000401d20 0 cycles 0
..... 6: 0000000000401d42 -> 0000000000401d3e 0 cycles 0
..... 7: 0000000000401d3c -> 0000000000401d42 0 cycles 0
..... 8: 0000000000401d44 -> 0000000000401d3c 0 cycles 0
..... 9: 0000000000401d3a -> 0000000000401d44 0 cycles 0
..... 10: 0000000000401d46 -> 0000000000401d3a 0 cycles 0
..... 11: 0000000000401d38 -> 0000000000401d46 0 cycles 0
..... 12: 0000000000401d48 -> 0000000000401d38 0 cycles 0
..... 13: 0000000000401d36 -> 0000000000401d48 0 cycles 0
..... 14: 0000000000401d4a -> 0000000000401d36 0 cycles 0
..... 15: 0000000000401d34 -> 0000000000401d4a 0 cycles 0
... thread: test:18230
...... dso: test
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220322221517.2510440-4-eranian@google.com
2022-03-22 15:15:07 -07:00
/* AMD Branch Sampling configuration */
# define MSR_AMD_DBG_EXTN_CFG 0xc000010f
# define MSR_AMD_SAMP_BR_FROM 0xc0010300
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# define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6)
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# define MSR_IA32_MPERF 0x000000e7
# define MSR_IA32_APERF 0x000000e8
# define MSR_IA32_THERM_CONTROL 0x0000019a
# define MSR_IA32_THERM_INTERRUPT 0x0000019b
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# define THERM_INT_HIGH_ENABLE (1 << 0)
# define THERM_INT_LOW_ENABLE (1 << 1)
# define THERM_INT_PLN_ENABLE (1 << 24)
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# define MSR_IA32_THERM_STATUS 0x0000019c
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# define THERM_STATUS_PROCHOT (1 << 0)
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# define THERM_STATUS_POWER_LIMIT (1 << 10)
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# define MSR_THERM2_CTL 0x0000019d
# define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
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# define MSR_IA32_MISC_ENABLE 0x000001a0
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# define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
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# define MSR_MISC_FEATURE_CONTROL 0x000001a4
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# define MSR_MISC_PWR_MGMT 0x000001aa
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# define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
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# define ENERGY_PERF_BIAS_PERFORMANCE 0
# define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
# define ENERGY_PERF_BIAS_NORMAL 6
# define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
# define ENERGY_PERF_BIAS_POWERSAVE 15
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# define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
# define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
# define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
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# define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
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# define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
# define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
# define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
# define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
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# define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
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2011-01-03 17:22:04 +05:30
/* Thermal Thresholds Support */
# define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
# define THERM_SHIFT_THRESHOLD0 8
# define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
# define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
# define THERM_SHIFT_THRESHOLD1 16
# define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
# define THERM_STATUS_THRESHOLD0 (1 << 6)
# define THERM_LOG_THRESHOLD0 (1 << 7)
# define THERM_STATUS_THRESHOLD1 (1 << 8)
# define THERM_LOG_THRESHOLD1 (1 << 9)
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/* MISC_ENABLE bits: architectural */
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# define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
# define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
# define MSR_IA32_MISC_ENABLE_TCC_BIT 1
# define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
# define MSR_IA32_MISC_ENABLE_EMON_BIT 7
# define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
# define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
# define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
# define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
# define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
# define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
# define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
# define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
# define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
# define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
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# define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
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# define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
# define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
# define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
# define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
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/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
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# define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
# define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
# define MSR_IA32_MISC_ENABLE_TM1_BIT 3
# define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
# define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
# define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
# define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
# define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
# define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
# define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
# define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
# define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
# define MSR_IA32_MISC_ENABLE_FERR_BIT 10
# define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
# define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
# define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
# define MSR_IA32_MISC_ENABLE_TM2_BIT 13
# define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
# define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
# define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
# define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
# define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
# define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
# define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
# define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
# define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
# define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
# define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
# define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
# define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
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/* MISC_FEATURES_ENABLES non-architectural features */
# define MSR_MISC_FEATURES_ENABLES 0x00000140
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# define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
# define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
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# define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
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# define MSR_IA32_TSC_DEADLINE 0x000006E0
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# define MSR_TSX_FORCE_ABORT 0x0000010F
# define MSR_TFA_RTM_FORCE_ABORT_BIT 0
# define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
x86/msr: Define new bits in TSX_FORCE_ABORT MSR
Intel client processors that support the IA32_TSX_FORCE_ABORT MSR
related to perf counter interaction [1] received a microcode update that
deprecates the Transactional Synchronization Extension (TSX) feature.
The bit FORCE_ABORT_RTM now defaults to 1, writes to this bit are
ignored. A new bit TSX_CPUID_CLEAR clears the TSX related CPUID bits.
The summary of changes to the IA32_TSX_FORCE_ABORT MSR are:
Bit 0: FORCE_ABORT_RTM (legacy bit, new default=1) Status bit that
indicates if RTM transactions are always aborted. This bit is
essentially !SDV_ENABLE_RTM(Bit 2). Writes to this bit are ignored.
Bit 1: TSX_CPUID_CLEAR (new bit, default=0) When set, CPUID.HLE = 0
and CPUID.RTM = 0.
Bit 2: SDV_ENABLE_RTM (new bit, default=0) When clear, XBEGIN will
always abort with EAX code 0. When set, XBEGIN will not be forced to
abort (but will always abort in SGX enclaves). This bit is intended to
be used on developer systems. If this bit is set, transactional
atomicity correctness is not certain. SDV = Software Development
Vehicle (SDV), i.e. developer systems.
Performance monitoring counter 3 is usable in all cases, regardless of
the value of above bits.
Add support for a new CPUID bit - CPUID.RTM_ALWAYS_ABORT (CPUID 7.EDX[11])
- to indicate the status of always abort behavior.
[1] [ bp: Look for document ID 604224, "Performance Monitoring Impact
of Intel Transactional Synchronization Extension Memory". Since
there's no way for us to have stable links to documents... ]
[ bp: Massage and extend commit message. ]
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
Link: https://lkml.kernel.org/r/9add61915b4a4eedad74fbd869107863a28b428e.1623704845.git-series.pawan.kumar.gupta@linux.intel.com
2021-06-14 14:12:22 -07:00
# define MSR_TFA_TSX_CPUID_CLEAR_BIT 1
# define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
# define MSR_TFA_SDV_ENABLE_RTM_BIT 2
# define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
2019-03-05 22:23:17 +01:00
2007-05-02 19:27:12 +02:00
/* P4/Xeon+ specific */
# define MSR_IA32_MCG_EAX 0x00000180
# define MSR_IA32_MCG_EBX 0x00000181
# define MSR_IA32_MCG_ECX 0x00000182
# define MSR_IA32_MCG_EDX 0x00000183
# define MSR_IA32_MCG_ESI 0x00000184
# define MSR_IA32_MCG_EDI 0x00000185
# define MSR_IA32_MCG_EBP 0x00000186
# define MSR_IA32_MCG_ESP 0x00000187
# define MSR_IA32_MCG_EFLAGS 0x00000188
# define MSR_IA32_MCG_EIP 0x00000189
# define MSR_IA32_MCG_RESERVED 0x0000018a
/* Pentium IV performance counter MSRs */
# define MSR_P4_BPU_PERFCTR0 0x00000300
# define MSR_P4_BPU_PERFCTR1 0x00000301
# define MSR_P4_BPU_PERFCTR2 0x00000302
# define MSR_P4_BPU_PERFCTR3 0x00000303
# define MSR_P4_MS_PERFCTR0 0x00000304
# define MSR_P4_MS_PERFCTR1 0x00000305
# define MSR_P4_MS_PERFCTR2 0x00000306
# define MSR_P4_MS_PERFCTR3 0x00000307
# define MSR_P4_FLAME_PERFCTR0 0x00000308
# define MSR_P4_FLAME_PERFCTR1 0x00000309
# define MSR_P4_FLAME_PERFCTR2 0x0000030a
# define MSR_P4_FLAME_PERFCTR3 0x0000030b
# define MSR_P4_IQ_PERFCTR0 0x0000030c
# define MSR_P4_IQ_PERFCTR1 0x0000030d
# define MSR_P4_IQ_PERFCTR2 0x0000030e
# define MSR_P4_IQ_PERFCTR3 0x0000030f
# define MSR_P4_IQ_PERFCTR4 0x00000310
# define MSR_P4_IQ_PERFCTR5 0x00000311
# define MSR_P4_BPU_CCCR0 0x00000360
# define MSR_P4_BPU_CCCR1 0x00000361
# define MSR_P4_BPU_CCCR2 0x00000362
# define MSR_P4_BPU_CCCR3 0x00000363
# define MSR_P4_MS_CCCR0 0x00000364
# define MSR_P4_MS_CCCR1 0x00000365
# define MSR_P4_MS_CCCR2 0x00000366
# define MSR_P4_MS_CCCR3 0x00000367
# define MSR_P4_FLAME_CCCR0 0x00000368
# define MSR_P4_FLAME_CCCR1 0x00000369
# define MSR_P4_FLAME_CCCR2 0x0000036a
# define MSR_P4_FLAME_CCCR3 0x0000036b
# define MSR_P4_IQ_CCCR0 0x0000036c
# define MSR_P4_IQ_CCCR1 0x0000036d
# define MSR_P4_IQ_CCCR2 0x0000036e
# define MSR_P4_IQ_CCCR3 0x0000036f
# define MSR_P4_IQ_CCCR4 0x00000370
# define MSR_P4_IQ_CCCR5 0x00000371
# define MSR_P4_ALF_ESCR0 0x000003ca
# define MSR_P4_ALF_ESCR1 0x000003cb
# define MSR_P4_BPU_ESCR0 0x000003b2
# define MSR_P4_BPU_ESCR1 0x000003b3
# define MSR_P4_BSU_ESCR0 0x000003a0
# define MSR_P4_BSU_ESCR1 0x000003a1
# define MSR_P4_CRU_ESCR0 0x000003b8
# define MSR_P4_CRU_ESCR1 0x000003b9
# define MSR_P4_CRU_ESCR2 0x000003cc
# define MSR_P4_CRU_ESCR3 0x000003cd
# define MSR_P4_CRU_ESCR4 0x000003e0
# define MSR_P4_CRU_ESCR5 0x000003e1
# define MSR_P4_DAC_ESCR0 0x000003a8
# define MSR_P4_DAC_ESCR1 0x000003a9
# define MSR_P4_FIRM_ESCR0 0x000003a4
# define MSR_P4_FIRM_ESCR1 0x000003a5
# define MSR_P4_FLAME_ESCR0 0x000003a6
# define MSR_P4_FLAME_ESCR1 0x000003a7
# define MSR_P4_FSB_ESCR0 0x000003a2
# define MSR_P4_FSB_ESCR1 0x000003a3
# define MSR_P4_IQ_ESCR0 0x000003ba
# define MSR_P4_IQ_ESCR1 0x000003bb
# define MSR_P4_IS_ESCR0 0x000003b4
# define MSR_P4_IS_ESCR1 0x000003b5
# define MSR_P4_ITLB_ESCR0 0x000003b6
# define MSR_P4_ITLB_ESCR1 0x000003b7
# define MSR_P4_IX_ESCR0 0x000003c8
# define MSR_P4_IX_ESCR1 0x000003c9
# define MSR_P4_MOB_ESCR0 0x000003aa
# define MSR_P4_MOB_ESCR1 0x000003ab
# define MSR_P4_MS_ESCR0 0x000003c0
# define MSR_P4_MS_ESCR1 0x000003c1
# define MSR_P4_PMH_ESCR0 0x000003ac
# define MSR_P4_PMH_ESCR1 0x000003ad
# define MSR_P4_RAT_ESCR0 0x000003bc
# define MSR_P4_RAT_ESCR1 0x000003bd
# define MSR_P4_SAAT_ESCR0 0x000003ae
# define MSR_P4_SAAT_ESCR1 0x000003af
# define MSR_P4_SSU_ESCR0 0x000003be
# define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
# define MSR_P4_TBPU_ESCR0 0x000003c2
# define MSR_P4_TBPU_ESCR1 0x000003c3
# define MSR_P4_TC_ESCR0 0x000003c4
# define MSR_P4_TC_ESCR1 0x000003c5
# define MSR_P4_U2L_ESCR0 0x000003b0
# define MSR_P4_U2L_ESCR1 0x000003b1
2010-03-18 18:33:12 +08:00
# define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
2007-05-02 19:27:12 +02:00
/* Intel Core-based CPU performance counters */
# define MSR_CORE_PERF_FIXED_CTR0 0x00000309
# define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
# define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
perf/x86/intel: Generic support for hardware TopDown metrics
Intro
=====
The TopDown Microarchitecture Analysis (TMA) Method is a structured
analysis methodology to identify critical performance bottlenecks in
out-of-order processors. Current perf has supported the method.
The method works well, but there is one problem. To collect the TopDown
events, several GP counters have to be used. If a user wants to collect
other events at the same time, the multiplexing probably be triggered,
which impacts the accuracy.
To free up the scarce GP counters, the hardware TopDown metrics feature
is introduced from Ice Lake. The hardware implements an additional
"metrics" register and a new Fixed Counter 3 that measures pipeline
"slots". The TopDown events can be calculated from them instead.
Events
======
The level 1 TopDown has four metrics. There is no event-code assigned to
the TopDown metrics. Four metric events are exported as separate perf
events, which map to the internal "metrics" counter register. Those
events do not exist in hardware, but can be allocated by the scheduler.
For the event mapping, a special 0x00 event code is used, which is
reserved for fake events. The metric events start from umask 0x10.
When setting up the metric events, they point to the Fixed Counter 3.
They have to be specially handled.
- Add the update_topdown_event() callback to read the additional metrics
MSR and generate the metrics.
- Add the set_topdown_event_period() callback to initialize metrics MSR
and the fixed counter 3.
- Add a variable n_metric_event to track the number of the accepted
metrics events. The sharing between multiple users of the same metric
without multiplexing is not allowed.
- Only enable/disable the fixed counter 3 when there are no other active
TopDown events, which avoid the unnecessary writing of the fixed
control register.
- Disable the PMU when reading the metrics event. The metrics MSR and
the fixed counter 3 are read separately. The values may be modified by
an NMI.
All four metric events don't support sampling. Since they will be
handled specially for event update, a flag PERF_X86_EVENT_TOPDOWN is
introduced to indicate this case.
The slots event can support both sampling and counting.
For counting, the flag is also applied.
For sampling, it will be handled normally as other normal events.
Groups
======
The slots event is required in a Topdown group.
To avoid reading the METRICS register multiple times, the metrics and
slots value can only be updated by slots event in a group.
All active slots and metrics events will be updated one time.
Therefore, the slots event must be before any metric events in a Topdown
group.
NMI
======
The METRICS related register may be overflow. The bit 48 of the STATUS
register will be set. If so, PERF_METRICS and Fixed counter 3 are
required to be reset. The patch also update all active slots and
metrics events in the NMI handler.
The update_topdown_event() has to read two registers separately. The
values may be modified by an NMI. PMU has to be disabled before calling
the function.
RDPMC
======
RDPMC is temporarily disabled. A later patch will enable it.
Suggested-by: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200723171117.9918-9-kan.liang@linux.intel.com
2020-07-23 10:11:11 -07:00
# define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
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# define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
# define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
# define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
# define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
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# define MSR_PERF_METRICS 0x00000329
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/* PERF_GLOBAL_OVF_CTL bits */
# define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
# define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
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# define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
# define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
# define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
# define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
2019-02-18 19:26:07 -05:00
2007-05-02 19:27:12 +02:00
/* Geode defined MSRs */
# define MSR_GEODE_BUSCONT_CONF0 0x00001900
2008-09-09 14:54:53 +08:00
/* Intel VT MSRs */
# define MSR_IA32_VMX_BASIC 0x00000480
# define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
# define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
# define MSR_IA32_VMX_EXIT_CTLS 0x00000483
# define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
# define MSR_IA32_VMX_MISC 0x00000485
# define MSR_IA32_VMX_CR0_FIXED0 0x00000486
# define MSR_IA32_VMX_CR0_FIXED1 0x00000487
# define MSR_IA32_VMX_CR4_FIXED0 0x00000488
# define MSR_IA32_VMX_CR4_FIXED1 0x00000489
# define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
# define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
# define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
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# define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
# define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
# define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
# define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
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# define MSR_IA32_VMX_VMFUNC 0x00000491
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# define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
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/* VMX_BASIC bits and bitmasks */
# define VMX_BASIC_VMCS_SIZE_SHIFT 32
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# define VMX_BASIC_TRUE_CTLS (1ULL << 55)
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# define VMX_BASIC_64 0x0001000000000000LLU
# define VMX_BASIC_MEM_TYPE_SHIFT 50
# define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
# define VMX_BASIC_MEM_TYPE_WB 6LLU
# define VMX_BASIC_INOUT 0x0040000000000000LLU
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/* MSR_IA32_VMX_MISC bits */
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# define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
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# define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
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# define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
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/* AMD-V MSRs */
# define MSR_VM_CR 0xc0010114
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# define MSR_VM_IGNNE 0xc0010115
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# define MSR_VM_HSAVE_PA 0xc0010117
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/* Hardware Feedback Interface */
# define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
# define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
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/* x2APIC locked status */
# define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD
# define LEGACY_XAPIC_DISABLED BIT(0) / *
* x2APIC mode is locked and
* disabling x2APIC will cause
* a # GP
*/
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# endif /* _ASM_X86_MSR_INDEX_H */
