2006-09-26 12:37:50 +04:00
/ *
* linux/ a r c h / a r m / m m / a r m 7 4 0 . S : u t i l i t y f u n c t i o n s f o r A R M 7 4 0
*
* Copyright ( C ) 2 0 0 4 - 2 0 0 6 H y o k S . C h o i ( h y o k . c h o i @samsung.com)
*
* This p r o g r a m i s f r e e s o f t w a r e ; you can redistribute it and/or modify
* it u n d e r t h e t e r m s o f t h e G N U G e n e r a l P u b l i c L i c e n s e v e r s i o n 2 a s
* published b y t h e F r e e S o f t w a r e F o u n d a t i o n .
*
* /
# include < l i n u x / l i n k a g e . h >
# include < l i n u x / i n i t . h >
# include < a s m / a s s e m b l e r . h >
# include < a s m / a s m - o f f s e t s . h >
2008-09-07 22:15:31 +04:00
# include < a s m / h w c a p . h >
2006-09-26 12:37:50 +04:00
# include < a s m / p g t a b l e - h w d e f . h >
# include < a s m / p g t a b l e . h >
# include < a s m / p t r a c e . h >
.text
/ *
* cpu_ a r m 7 4 0 _ p r o c _ i n i t ( )
* cpu_ a r m 7 4 0 _ d o _ i d l e ( )
* cpu_ a r m 7 4 0 _ d c a c h e _ c l e a n _ a r e a ( )
* cpu_ a r m 7 4 0 _ s w i t c h _ m m ( )
*
* These a r e n o t r e q u i r e d .
* /
ENTRY( c p u _ a r m 7 4 0 _ p r o c _ i n i t )
ENTRY( c p u _ a r m 7 4 0 _ d o _ i d l e )
ENTRY( c p u _ a r m 7 4 0 _ d c a c h e _ c l e a n _ a r e a )
ENTRY( c p u _ a r m 7 4 0 _ s w i t c h _ m m )
mov p c , l r
/ *
* cpu_ a r m 7 4 0 _ p r o c _ f i n ( )
* /
ENTRY( c p u _ a r m 7 4 0 _ p r o c _ f i n )
mrc p15 , 0 , r0 , c1 , c0 , 0
bic r0 , r0 , #0x3f000000 @ bank/f/lock/s
bic r0 , r0 , #0x0000000c @ w-buffer/cache
mcr p15 , 0 , r0 , c1 , c0 , 0 @ disable caches
2010-07-26 15:22:12 +04:00
mov p c , l r
2006-09-26 12:37:50 +04:00
/ *
* cpu_ a r m 7 4 0 _ r e s e t ( l o c )
* Params : r0 = a d d r e s s t o j u m p t o
* Notes : T h i s s e t s u p e v e r y t h i n g f o r a r e s e t
* /
ENTRY( c p u _ a r m 7 4 0 _ r e s e t )
mov i p , #0
mcr p15 , 0 , i p , c7 , c0 , 0 @ invalidate cache
mrc p15 , 0 , i p , c1 , c0 , 0 @ get ctrl register
bic i p , i p , #0x0000000c @ ............wc..
mcr p15 , 0 , i p , c1 , c0 , 0 @ ctrl register
mov p c , r0
2010-10-01 18:37:05 +04:00
_ _ CPUINIT
2006-09-26 12:37:50 +04:00
.type _ _ arm7 4 0 _ s e t u p , #f u n c t i o n
__arm740_setup :
mov r0 , #0
mcr p15 , 0 , r0 , c7 , c0 , 0 @ invalidate caches
mcr p15 , 0 , r0 , c6 , c3 @ disable area 3~7
mcr p15 , 0 , r0 , c6 , c4
mcr p15 , 0 , r0 , c6 , c5
mcr p15 , 0 , r0 , c6 , c6
mcr p15 , 0 , r0 , c6 , c7
mov r0 , #0x0000003F @ base = 0, size = 4GB
mcr p15 , 0 , r0 , c6 , c0 @ set area 0, default
ldr r0 , = ( C O N F I G _ D R A M _ B A S E & 0 x F F F F F 0 0 0 ) @ base[31:12] of RAM
ldr r1 , = ( C O N F I G _ D R A M _ S I Z E > > 1 2 ) @ size of RAM (must be >= 4KB)
mov r2 , #10 @ 11 is the minimum (4KB)
1 : add r2 , r2 , #1 @ area size *= 2
mov r1 , r1 , l s r #1
bne 1 b @ count not zero r-shift
orr r0 , r0 , r2 , l s l #1 @ the area register value
orr r0 , r0 , #1 @ set enable bit
mcr p15 , 0 , r0 , c6 , c1 @ set area 1, RAM
ldr r0 , = ( C O N F I G _ F L A S H _ M E M _ B A S E & 0 x F F F F F 0 0 0 ) @ base[31:12] of FLASH
ldr r1 , = ( C O N F I G _ F L A S H _ S I Z E > > 1 2 ) @ size of FLASH (must be >= 4KB)
mov r2 , #10 @ 11 is the minimum (4KB)
1 : add r2 , r2 , #1 @ area size *= 2
mov r1 , r1 , l s r #1
bne 1 b @ count not zero r-shift
orr r0 , r0 , r2 , l s l #1 @ the area register value
orr r0 , r0 , #1 @ set enable bit
mcr p15 , 0 , r0 , c6 , c2 @ set area 2, ROM/FLASH
mov r0 , #0x06
mcr p15 , 0 , r0 , c2 , c0 @ Region 1&2 cacheable
# ifdef C O N F I G _ C P U _ D C A C H E _ W R I T E T H R O U G H
mov r0 , #0x00 @ disable whole write buffer
# else
mov r0 , #0x02 @ Region 1 write bufferred
# endif
mcr p15 , 0 , r0 , c3 , c0
mov r0 , #0x10000
sub r0 , r0 , #1 @ r0 = 0xffff
mcr p15 , 0 , r0 , c5 , c0 @ all read/write access
mrc p15 , 0 , r0 , c1 , c0 @ get control register
bic r0 , r0 , #0x3F000000 @ set to standard caching mode
@ need some benchmark
orr r0 , r0 , #0x0000000d @ MPU/Cache/WB
mov p c , l r
.size _ _ arm7 4 0 _ s e t u p , . - _ _ a r m 7 4 0 _ s e t u p
_ _ INITDATA
/ *
* Purpose : F u n c t i o n p o i n t e r s u s e d t o a c c e s s a b o v e f u n c t i o n s - a l l c a l l s
* come t h r o u g h t h e s e
* /
.type 7 4 0 _ p r o c e s s o r _ f u n c t i o n s , #o b j e c t
ENTRY( a r m 7 4 0 _ p r o c e s s o r _ f u n c t i o n s )
.word v4t_late_abort
2009-09-25 16:39:47 +04:00
.word legacy_pabort
2006-09-26 12:37:50 +04:00
.word cpu_arm740_proc_init
.word cpu_arm740_proc_fin
.word cpu_arm740_reset
.word cpu_arm740_do_idle
.word cpu_arm740_dcache_clean_area
.word cpu_arm740_switch_mm
.word 0 @ cpu_*_set_pte
.size 7 4 0 _ p r o c e s s o r _ f u n c t i o n s , . - a r m 7 4 0 _ p r o c e s s o r _ f u n c t i o n s
.section " .rodata "
.type _ a r c h _ n a m e , #o b j e c t
cpu_arch_name :
.asciz " armv4 "
.size _ a r c h _ n a m e , . - c p u _ a r c h _ n a m e
.type _ e l f _ n a m e , #o b j e c t
cpu_elf_name :
.asciz " v4 "
.size _ e l f _ n a m e , . - c p u _ e l f _ n a m e
.type _ a r m 7 4 0 _ n a m e , #o b j e c t
cpu_arm740_name :
.ascii " ARM7 4 0 T "
.size _ a r m 7 4 0 _ n a m e , . - c p u _ a r m 7 4 0 _ n a m e
.align
.section " .proc .info .init " , # alloc, #e x e c i n s t r
.type _ _ arm7 4 0 _ p r o c _ i n f o ,#o b j e c t
__arm740_proc_info :
.long 0x41807400
.long 0xfffffff0
.long 0
b _ _ a r m 7 4 0 _ s e t u p
.long cpu_arch_name
.long cpu_elf_name
.long HWCAP_SWP | HWCAP_ H A L F | H W C A P _ 2 6 B I T
.long cpu_arm740_name
.long arm740_processor_functions
.long 0
.long 0
.long v3_cache_fns @ cache model
.size _ _ arm7 4 0 _ p r o c _ i n f o , . - _ _ a r m 7 4 0 _ p r o c _ i n f o
