2007-07-09 22:56:42 +04:00
#
# Generic algorithms support
#
config XOR_BLOCKS
tristate
2005-04-17 02:20:36 +04:00
#
async_tx: add the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client that smooths over
the details of different hardware offload engine implementations. Code
that is written to the api can optimize for asynchronous operation and the
api will fit the chain of operations to the available offload resources.
I imagine that any piece of ADMA hardware would register with the
'async_*' subsystem, and a call to async_X would be routed as
appropriate, or be run in-line. - Neil Brown
async_tx exploits the capabilities of struct dma_async_tx_descriptor to
provide an api of the following general format:
struct dma_async_tx_descriptor *
async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
dma_async_tx_callback cb_fn, void *cb_param)
{
struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
struct dma_device *device = chan ? chan->device : NULL;
int int_en = cb_fn ? 1 : 0;
struct dma_async_tx_descriptor *tx = device ?
device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
if (tx) { /* run <operation> asynchronously */
...
tx->tx_set_dest(addr, tx, index);
...
tx->tx_set_src(addr, tx, index);
...
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
} else { /* run <operation> synchronously */
...
<operation>
...
async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
}
return tx;
}
async_tx_find_channel() returns a capable channel from its pool. The
channel pool is organized as a per-cpu array of channel pointers. The
async_tx_rebalance() routine is tasked with managing these arrays. In the
uniprocessor case async_tx_rebalance() tries to spread responsibility
evenly over channels of similar capabilities. For example if there are two
copy+xor channels, one will handle copy operations and the other will
handle xor. In the SMP case async_tx_rebalance() attempts to spread the
operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
dependency is specified async_tx_find_channel defaults to keeping the
operation on the same channel. A xor->copy->xor chain will stay on one
channel if it supports both operation types, otherwise the transaction will
transition between a copy and a xor resource.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided in a later
commit. With the iop-adma driver and async_tx, raid456 is able to offload
copy, xor, and xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' on iop342 CPU
utilization drops from ~50% to ~15% during a 'resync' while the speed
according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
The tiobench command line used for testing was: tiobench --size 2048
--block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
Details:
* if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
async_tx_find_channel a static inline routine that always returns NULL
* when a callback is specified for a given transaction an interrupt will
fire at operation completion time and the callback will occur in a
tasklet. if the the channel does not support interrupts then a live
polling wait will be performed
* the api is written as a dmaengine client that requests all available
channels
* In support of dependencies the api implicitly schedules channel-switch
interrupts. The interrupt triggers the cleanup tasklet which causes
pending operations to be scheduled on the next channel
* Xor engines treat an xor destination address differently than a software
xor routine. To the software routine the destination address is an implied
source, whereas engines treat it as a write-only destination. This patch
modifies the xor_blocks routine to take a an explicit destination address
to mirror the hardware.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
* don't use inline in C files, Adrian Bunk
* select the API when MD is enabled
* BUG_ON xor source counts <= 1
* implicitly handle hardware concerns like channel switching and
interrupts, Neil Brown
* remove the per operation type list, and distribute operation capabilities
evenly amongst the available channels
* simplify async_tx_find_channel to optimize the fast path
* introduce the channel_table_initialized flag to prevent early calls to
the api
* reorganize the code to mimic crypto
* include mm.h as not all archs include it in dma-mapping.h
* make the Kconfig options non-user visible, Adrian Bunk
* move async_tx under crypto since it is meant as 'core' functionality, and
the two may share algorithms in the future
* move large inline functions into c files
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-By: NeilBrown <neilb@suse.de>
2007-01-02 21:10:44 +03:00
# async_tx api: hardware offloaded memory transfer/transform support
2005-04-17 02:20:36 +04:00
#
async_tx: add the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client that smooths over
the details of different hardware offload engine implementations. Code
that is written to the api can optimize for asynchronous operation and the
api will fit the chain of operations to the available offload resources.
I imagine that any piece of ADMA hardware would register with the
'async_*' subsystem, and a call to async_X would be routed as
appropriate, or be run in-line. - Neil Brown
async_tx exploits the capabilities of struct dma_async_tx_descriptor to
provide an api of the following general format:
struct dma_async_tx_descriptor *
async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
dma_async_tx_callback cb_fn, void *cb_param)
{
struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
struct dma_device *device = chan ? chan->device : NULL;
int int_en = cb_fn ? 1 : 0;
struct dma_async_tx_descriptor *tx = device ?
device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
if (tx) { /* run <operation> asynchronously */
...
tx->tx_set_dest(addr, tx, index);
...
tx->tx_set_src(addr, tx, index);
...
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
} else { /* run <operation> synchronously */
...
<operation>
...
async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
}
return tx;
}
async_tx_find_channel() returns a capable channel from its pool. The
channel pool is organized as a per-cpu array of channel pointers. The
async_tx_rebalance() routine is tasked with managing these arrays. In the
uniprocessor case async_tx_rebalance() tries to spread responsibility
evenly over channels of similar capabilities. For example if there are two
copy+xor channels, one will handle copy operations and the other will
handle xor. In the SMP case async_tx_rebalance() attempts to spread the
operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
dependency is specified async_tx_find_channel defaults to keeping the
operation on the same channel. A xor->copy->xor chain will stay on one
channel if it supports both operation types, otherwise the transaction will
transition between a copy and a xor resource.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided in a later
commit. With the iop-adma driver and async_tx, raid456 is able to offload
copy, xor, and xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' on iop342 CPU
utilization drops from ~50% to ~15% during a 'resync' while the speed
according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
The tiobench command line used for testing was: tiobench --size 2048
--block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
Details:
* if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
async_tx_find_channel a static inline routine that always returns NULL
* when a callback is specified for a given transaction an interrupt will
fire at operation completion time and the callback will occur in a
tasklet. if the the channel does not support interrupts then a live
polling wait will be performed
* the api is written as a dmaengine client that requests all available
channels
* In support of dependencies the api implicitly schedules channel-switch
interrupts. The interrupt triggers the cleanup tasklet which causes
pending operations to be scheduled on the next channel
* Xor engines treat an xor destination address differently than a software
xor routine. To the software routine the destination address is an implied
source, whereas engines treat it as a write-only destination. This patch
modifies the xor_blocks routine to take a an explicit destination address
to mirror the hardware.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
* don't use inline in C files, Adrian Bunk
* select the API when MD is enabled
* BUG_ON xor source counts <= 1
* implicitly handle hardware concerns like channel switching and
interrupts, Neil Brown
* remove the per operation type list, and distribute operation capabilities
evenly amongst the available channels
* simplify async_tx_find_channel to optimize the fast path
* introduce the channel_table_initialized flag to prevent early calls to
the api
* reorganize the code to mimic crypto
* include mm.h as not all archs include it in dma-mapping.h
* make the Kconfig options non-user visible, Adrian Bunk
* move async_tx under crypto since it is meant as 'core' functionality, and
the two may share algorithms in the future
* move large inline functions into c files
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-By: NeilBrown <neilb@suse.de>
2007-01-02 21:10:44 +03:00
source "crypto/async_tx/Kconfig"
2005-04-17 02:20:36 +04:00
async_tx: add the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client that smooths over
the details of different hardware offload engine implementations. Code
that is written to the api can optimize for asynchronous operation and the
api will fit the chain of operations to the available offload resources.
I imagine that any piece of ADMA hardware would register with the
'async_*' subsystem, and a call to async_X would be routed as
appropriate, or be run in-line. - Neil Brown
async_tx exploits the capabilities of struct dma_async_tx_descriptor to
provide an api of the following general format:
struct dma_async_tx_descriptor *
async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
dma_async_tx_callback cb_fn, void *cb_param)
{
struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
struct dma_device *device = chan ? chan->device : NULL;
int int_en = cb_fn ? 1 : 0;
struct dma_async_tx_descriptor *tx = device ?
device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
if (tx) { /* run <operation> asynchronously */
...
tx->tx_set_dest(addr, tx, index);
...
tx->tx_set_src(addr, tx, index);
...
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
} else { /* run <operation> synchronously */
...
<operation>
...
async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
}
return tx;
}
async_tx_find_channel() returns a capable channel from its pool. The
channel pool is organized as a per-cpu array of channel pointers. The
async_tx_rebalance() routine is tasked with managing these arrays. In the
uniprocessor case async_tx_rebalance() tries to spread responsibility
evenly over channels of similar capabilities. For example if there are two
copy+xor channels, one will handle copy operations and the other will
handle xor. In the SMP case async_tx_rebalance() attempts to spread the
operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
dependency is specified async_tx_find_channel defaults to keeping the
operation on the same channel. A xor->copy->xor chain will stay on one
channel if it supports both operation types, otherwise the transaction will
transition between a copy and a xor resource.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided in a later
commit. With the iop-adma driver and async_tx, raid456 is able to offload
copy, xor, and xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' on iop342 CPU
utilization drops from ~50% to ~15% during a 'resync' while the speed
according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
The tiobench command line used for testing was: tiobench --size 2048
--block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
Details:
* if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
async_tx_find_channel a static inline routine that always returns NULL
* when a callback is specified for a given transaction an interrupt will
fire at operation completion time and the callback will occur in a
tasklet. if the the channel does not support interrupts then a live
polling wait will be performed
* the api is written as a dmaengine client that requests all available
channels
* In support of dependencies the api implicitly schedules channel-switch
interrupts. The interrupt triggers the cleanup tasklet which causes
pending operations to be scheduled on the next channel
* Xor engines treat an xor destination address differently than a software
xor routine. To the software routine the destination address is an implied
source, whereas engines treat it as a write-only destination. This patch
modifies the xor_blocks routine to take a an explicit destination address
to mirror the hardware.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
* don't use inline in C files, Adrian Bunk
* select the API when MD is enabled
* BUG_ON xor source counts <= 1
* implicitly handle hardware concerns like channel switching and
interrupts, Neil Brown
* remove the per operation type list, and distribute operation capabilities
evenly amongst the available channels
* simplify async_tx_find_channel to optimize the fast path
* introduce the channel_table_initialized flag to prevent early calls to
the api
* reorganize the code to mimic crypto
* include mm.h as not all archs include it in dma-mapping.h
* make the Kconfig options non-user visible, Adrian Bunk
* move async_tx under crypto since it is meant as 'core' functionality, and
the two may share algorithms in the future
* move large inline functions into c files
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-By: NeilBrown <neilb@suse.de>
2007-01-02 21:10:44 +03:00
#
# Cryptographic API Configuration
#
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menuconfig CRYPTO
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tristate "Cryptographic API"
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help
This option provides the core Cryptographic API.
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if CRYPTO
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comment "Crypto core or helper"
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config CRYPTO_FIPS
bool "FIPS 200 compliance"
help
This options enables the fips boot option which is
required if you want to system to operate in a FIPS 200
certification. You should say no unless you know what
this is.
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config CRYPTO_ALGAPI
tristate
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select CRYPTO_ALGAPI2
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help
This option provides the API for cryptographic algorithms.
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config CRYPTO_ALGAPI2
tristate
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config CRYPTO_AEAD
tristate
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select CRYPTO_AEAD2
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select CRYPTO_ALGAPI
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config CRYPTO_AEAD2
tristate
select CRYPTO_ALGAPI2
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config CRYPTO_BLKCIPHER
tristate
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select CRYPTO_BLKCIPHER2
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select CRYPTO_ALGAPI
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config CRYPTO_BLKCIPHER2
tristate
select CRYPTO_ALGAPI2
select CRYPTO_RNG2
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select CRYPTO_WORKQUEUE
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config CRYPTO_HASH
tristate
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select CRYPTO_HASH2
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select CRYPTO_ALGAPI
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config CRYPTO_HASH2
tristate
select CRYPTO_ALGAPI2
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config CRYPTO_RNG
tristate
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select CRYPTO_RNG2
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select CRYPTO_ALGAPI
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config CRYPTO_RNG2
tristate
select CRYPTO_ALGAPI2
crypto: compress - Add pcomp interface
The current "comp" crypto interface supports one-shot (de)compression only,
i.e. the whole data buffer to be (de)compressed must be passed at once, and
the whole (de)compressed data buffer will be received at once.
In several use-cases (e.g. compressed file systems that store files in big
compressed blocks), this workflow is not suitable.
Furthermore, the "comp" type doesn't provide for the configuration of
(de)compression parameters, and always allocates workspace memory for both
compression and decompression, which may waste memory.
To solve this, add a "pcomp" partial (de)compression interface that provides
the following operations:
- crypto_compress_{init,update,final}() for compression,
- crypto_decompress_{init,update,final}() for decompression,
- crypto_{,de}compress_setup(), to configure (de)compression parameters
(incl. allocating workspace memory).
The (de)compression methods take a struct comp_request, which was mimicked
after the z_stream object in zlib, and contains buffer pointer and length
pairs for input and output.
The setup methods take an opaque parameter pointer and length pair. Parameters
are supposed to be encoded using netlink attributes, whose meanings depend on
the actual (name of the) (de)compression algorithm.
Signed-off-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2009-03-04 10:05:33 +03:00
config CRYPTO_PCOMP
tristate
select CRYPTO_ALGAPI2
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config CRYPTO_MANAGER
tristate "Cryptographic algorithm manager"
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select CRYPTO_MANAGER2
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help
Create default cryptographic template instantiations such as
cbc(aes).
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config CRYPTO_MANAGER2
def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y)
select CRYPTO_AEAD2
select CRYPTO_HASH2
select CRYPTO_BLKCIPHER2
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config CRYPTO_GF128MUL
tristate "GF(2^128) multiplication functions (EXPERIMENTAL)"
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depends on EXPERIMENTAL
help
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Efficient table driven implementation of multiplications in the
field GF(2^128). This is needed by some cypher modes. This
option will be selected automatically if you select such a
cipher mode. Only select this option by hand if you expect to load
an external module that requires these functions.
2006-10-28 07:15:24 +04:00
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config CRYPTO_NULL
tristate "Null algorithms"
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select CRYPTO_ALGAPI
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select CRYPTO_BLKCIPHER
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select CRYPTO_HASH
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help
These are 'Null' algorithms, used by IPsec, which do nothing.
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config CRYPTO_WORKQUEUE
tristate
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config CRYPTO_CRYPTD
tristate "Software async crypto daemon"
select CRYPTO_BLKCIPHER
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select CRYPTO_HASH
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select CRYPTO_MANAGER
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select CRYPTO_WORKQUEUE
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help
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This is a generic software asynchronous crypto daemon that
converts an arbitrary synchronous software crypto algorithm
into an asynchronous algorithm that executes in a kernel thread.
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config CRYPTO_AUTHENC
tristate "Authenc support"
select CRYPTO_AEAD
select CRYPTO_BLKCIPHER
select CRYPTO_MANAGER
select CRYPTO_HASH
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help
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Authenc: Combined mode wrapper for IPsec.
This is required for IPSec.
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config CRYPTO_TEST
tristate "Testing module"
depends on m
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select CRYPTO_MANAGER
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help
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Quick & dirty crypto test module.
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comment "Authenticated Encryption with Associated Data"
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config CRYPTO_CCM
tristate "CCM support"
select CRYPTO_CTR
select CRYPTO_AEAD
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help
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Support for Counter with CBC MAC. Required for IPsec.
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config CRYPTO_GCM
tristate "GCM/GMAC support"
select CRYPTO_CTR
select CRYPTO_AEAD
select CRYPTO_GF128MUL
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help
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Support for Galois/Counter Mode (GCM) and Galois Message
Authentication Code (GMAC). Required for IPSec.
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config CRYPTO_SEQIV
tristate "Sequence Number IV Generator"
select CRYPTO_AEAD
select CRYPTO_BLKCIPHER
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select CRYPTO_RNG
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help
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This IV generator generates an IV based on a sequence number by
xoring it with a salt. This algorithm is mainly useful for CTR
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comment "Block modes"
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config CRYPTO_CBC
tristate "CBC support"
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select CRYPTO_BLKCIPHER
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select CRYPTO_MANAGER
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help
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CBC: Cipher Block Chaining mode
This block cipher algorithm is required for IPSec.
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config CRYPTO_CTR
tristate "CTR support"
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select CRYPTO_BLKCIPHER
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select CRYPTO_SEQIV
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select CRYPTO_MANAGER
2006-09-21 05:44:08 +04:00
help
2008-04-05 17:04:48 +04:00
CTR: Counter mode
2006-09-21 05:44:08 +04:00
This block cipher algorithm is required for IPSec.
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config CRYPTO_CTS
tristate "CTS support"
select CRYPTO_BLKCIPHER
help
CTS: Cipher Text Stealing
This is the Cipher Text Stealing mode as described by
Section 8 of rfc2040 and referenced by rfc3962.
(rfc3962 includes errata information in its Appendix A)
This mode is required for Kerberos gss mechanism support
for AES encryption.
config CRYPTO_ECB
tristate "ECB support"
2006-12-16 04:09:02 +03:00
select CRYPTO_BLKCIPHER
select CRYPTO_MANAGER
help
2008-04-05 17:04:48 +04:00
ECB: Electronic CodeBook mode
This is the simplest block cipher algorithm. It simply encrypts
the input block by block.
2006-12-16 04:09:02 +03:00
2006-11-26 01:43:10 +03:00
config CRYPTO_LRW
tristate "LRW support (EXPERIMENTAL)"
depends on EXPERIMENTAL
select CRYPTO_BLKCIPHER
select CRYPTO_MANAGER
select CRYPTO_GF128MUL
help
LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable
narrow block cipher mode for dm-crypt. Use it with cipher
specification string aes-lrw-benbi, the key must be 256, 320 or 384.
The first 128, 192 or 256 bits in the key are used for AES and the
rest is used to tie each cipher block to its logical position.
2008-04-05 17:04:48 +04:00
config CRYPTO_PCBC
tristate "PCBC support"
select CRYPTO_BLKCIPHER
select CRYPTO_MANAGER
help
PCBC: Propagating Cipher Block Chaining mode
This block cipher algorithm is required for RxRPC.
2007-09-19 16:23:13 +04:00
config CRYPTO_XTS
tristate "XTS support (EXPERIMENTAL)"
depends on EXPERIMENTAL
select CRYPTO_BLKCIPHER
select CRYPTO_MANAGER
select CRYPTO_GF128MUL
help
XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain,
key size 256, 384 or 512 bits. This implementation currently
can't handle a sectorsize which is not a multiple of 16 bytes.
2008-04-05 17:04:48 +04:00
comment "Hash modes"
config CRYPTO_HMAC
tristate "HMAC support"
select CRYPTO_HASH
[CRYPTO] ctr: Add CTR (Counter) block cipher mode
This patch implements CTR mode for IPsec.
It is based off of RFC 3686.
Please note:
1. CTR turns a block cipher into a stream cipher.
Encryption is done in blocks, however the last block
may be a partial block.
A "counter block" is encrypted, creating a keystream
that is xor'ed with the plaintext. The counter portion
of the counter block is incremented after each block
of plaintext is encrypted.
Decryption is performed in same manner.
2. The CTR counterblock is composed of,
nonce + IV + counter
The size of the counterblock is equivalent to the
blocksize of the cipher.
sizeof(nonce) + sizeof(IV) + sizeof(counter) = blocksize
The CTR template requires the name of the cipher
algorithm, the sizeof the nonce, and the sizeof the iv.
ctr(cipher,sizeof_nonce,sizeof_iv)
So for example,
ctr(aes,4,8)
specifies the counterblock will be composed of 4 bytes
from a nonce, 8 bytes from the iv, and 4 bytes for counter
since aes has a blocksize of 16 bytes.
3. The counter portion of the counter block is stored
in big endian for conformance to rfc 3686.
Signed-off-by: Joy Latten <latten@austin.ibm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-10-23 04:50:32 +04:00
select CRYPTO_MANAGER
help
2008-04-05 17:04:48 +04:00
HMAC: Keyed-Hashing for Message Authentication (RFC2104).
This is required for IPSec.
[CRYPTO] ctr: Add CTR (Counter) block cipher mode
This patch implements CTR mode for IPsec.
It is based off of RFC 3686.
Please note:
1. CTR turns a block cipher into a stream cipher.
Encryption is done in blocks, however the last block
may be a partial block.
A "counter block" is encrypted, creating a keystream
that is xor'ed with the plaintext. The counter portion
of the counter block is incremented after each block
of plaintext is encrypted.
Decryption is performed in same manner.
2. The CTR counterblock is composed of,
nonce + IV + counter
The size of the counterblock is equivalent to the
blocksize of the cipher.
sizeof(nonce) + sizeof(IV) + sizeof(counter) = blocksize
The CTR template requires the name of the cipher
algorithm, the sizeof the nonce, and the sizeof the iv.
ctr(cipher,sizeof_nonce,sizeof_iv)
So for example,
ctr(aes,4,8)
specifies the counterblock will be composed of 4 bytes
from a nonce, 8 bytes from the iv, and 4 bytes for counter
since aes has a blocksize of 16 bytes.
3. The counter portion of the counter block is stored
in big endian for conformance to rfc 3686.
Signed-off-by: Joy Latten <latten@austin.ibm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-10-23 04:50:32 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_XCBC
tristate "XCBC support"
depends on EXPERIMENTAL
select CRYPTO_HASH
select CRYPTO_MANAGER
2008-03-24 16:26:16 +03:00
help
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XCBC: Keyed-Hashing with encryption algorithm
http://www.ietf.org/rfc/rfc3566.txt
http://csrc.nist.gov/encryption/modes/proposedmodes/
xcbc-mac/xcbc-mac-spec.pdf
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comment "Digest"
2007-11-26 17:24:11 +03:00
2008-04-05 17:04:48 +04:00
config CRYPTO_CRC32C
tristate "CRC32c CRC algorithm"
2008-07-08 16:54:28 +04:00
select CRYPTO_HASH
2007-12-12 15:25:13 +03:00
help
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Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used
by iSCSI for header and data digests and by others.
2008-11-07 10:11:47 +03:00
See Castagnoli93. Module will be crc32c.
2007-12-12 15:25:13 +03:00
2008-08-07 05:57:03 +04:00
config CRYPTO_CRC32C_INTEL
tristate "CRC32c INTEL hardware acceleration"
depends on X86
select CRYPTO_HASH
help
In Intel processor with SSE4.2 supported, the processor will
support CRC32C implementation using hardware accelerated CRC32
instruction. This option will create 'crc32c-intel' module,
which will enable any routine to use the CRC32 instruction to
gain performance compared with software implementation.
Module will be crc32c-intel.
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config CRYPTO_MD4
tristate "MD4 digest algorithm"
2008-12-03 14:55:27 +03:00
select CRYPTO_HASH
2007-04-16 14:49:20 +04:00
help
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MD4 message digest algorithm (RFC1320).
2007-04-16 14:49:20 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_MD5
tristate "MD5 digest algorithm"
2008-12-03 14:57:12 +03:00
select CRYPTO_HASH
2005-04-17 02:20:36 +04:00
help
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MD5 message digest algorithm (RFC1321).
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_MICHAEL_MIC
tristate "Michael MIC keyed digest algorithm"
2008-12-07 14:35:38 +03:00
select CRYPTO_HASH
2006-12-16 04:13:14 +03:00
help
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Michael MIC is used for message integrity protection in TKIP
(IEEE 802.11i). This algorithm is required for TKIP, but it
should not be used for other purposes because of the weakness
of the algorithm.
2006-12-16 04:13:14 +03:00
2008-05-07 18:17:37 +04:00
config CRYPTO_RMD128
2008-07-16 15:28:00 +04:00
tristate "RIPEMD-128 digest algorithm"
2008-11-08 04:10:40 +03:00
select CRYPTO_HASH
2008-07-16 15:28:00 +04:00
help
RIPEMD-128 (ISO/IEC 10118-3:2004).
2008-05-07 18:17:37 +04:00
2008-07-16 15:28:00 +04:00
RIPEMD-128 is a 128-bit cryptographic hash function. It should only
to be used as a secure replacement for RIPEMD. For other use cases
RIPEMD-160 should be used.
2008-05-07 18:17:37 +04:00
2008-07-16 15:28:00 +04:00
Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel.
See <http://home.esat.kuleuven.be/~bosselae/ripemd160.html>
2008-05-07 18:17:37 +04:00
config CRYPTO_RMD160
2008-07-16 15:28:00 +04:00
tristate "RIPEMD-160 digest algorithm"
2008-11-08 04:18:51 +03:00
select CRYPTO_HASH
2008-07-16 15:28:00 +04:00
help
RIPEMD-160 (ISO/IEC 10118-3:2004).
2008-05-07 18:17:37 +04:00
2008-07-16 15:28:00 +04:00
RIPEMD-160 is a 160-bit cryptographic hash function. It is intended
to be used as a secure replacement for the 128-bit hash functions
MD4, MD5 and it's predecessor RIPEMD
(not to be confused with RIPEMD-128).
2008-05-07 18:17:37 +04:00
2008-07-16 15:28:00 +04:00
It's speed is comparable to SHA1 and there are no known attacks
against RIPEMD-160.
2008-05-09 17:30:27 +04:00
2008-07-16 15:28:00 +04:00
Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel.
See <http://home.esat.kuleuven.be/~bosselae/ripemd160.html>
2008-05-09 17:30:27 +04:00
config CRYPTO_RMD256
2008-07-16 15:28:00 +04:00
tristate "RIPEMD-256 digest algorithm"
2008-11-08 04:58:10 +03:00
select CRYPTO_HASH
2008-07-16 15:28:00 +04:00
help
RIPEMD-256 is an optional extension of RIPEMD-128 with a
256 bit hash. It is intended for applications that require
longer hash-results, without needing a larger security level
(than RIPEMD-128).
2008-05-09 17:30:27 +04:00
2008-07-16 15:28:00 +04:00
Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel.
See <http://home.esat.kuleuven.be/~bosselae/ripemd160.html>
2008-05-09 17:30:27 +04:00
config CRYPTO_RMD320
2008-07-16 15:28:00 +04:00
tristate "RIPEMD-320 digest algorithm"
2008-11-08 05:11:09 +03:00
select CRYPTO_HASH
2008-07-16 15:28:00 +04:00
help
RIPEMD-320 is an optional extension of RIPEMD-160 with a
320 bit hash. It is intended for applications that require
longer hash-results, without needing a larger security level
(than RIPEMD-160).
2008-05-09 17:30:27 +04:00
2008-07-16 15:28:00 +04:00
Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel.
See <http://home.esat.kuleuven.be/~bosselae/ripemd160.html>
2008-05-07 18:17:37 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_SHA1
tristate "SHA1 digest algorithm"
2008-12-02 16:08:20 +03:00
select CRYPTO_HASH
2005-04-17 02:20:36 +04:00
help
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SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_SHA256
tristate "SHA224 and SHA256 digest algorithm"
2008-12-03 14:57:49 +03:00
select CRYPTO_HASH
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
SHA256 secure hash standard (DFIPS 180-2).
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
This version of SHA implements a 256 bit hash with 128 bits of
security against collision attacks.
2006-06-20 14:37:23 +04:00
2008-07-16 15:28:00 +04:00
This code also includes SHA-224, a 224 bit hash with 112 bits
of security against collision attacks.
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config CRYPTO_SHA512
tristate "SHA384 and SHA512 digest algorithms"
2008-12-17 08:49:02 +03:00
select CRYPTO_HASH
2006-06-20 14:59:16 +04:00
help
2008-04-05 17:04:48 +04:00
SHA512 secure hash standard (DFIPS 180-2).
2006-06-20 14:59:16 +04:00
2008-04-05 17:04:48 +04:00
This version of SHA implements a 512 bit hash with 256 bits of
security against collision attacks.
2006-06-20 14:59:16 +04:00
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This code also includes SHA-384, a 384 bit hash with 192 bits
of security against collision attacks.
2006-06-20 14:59:16 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_TGR192
tristate "Tiger digest algorithms"
2008-12-03 14:58:32 +03:00
select CRYPTO_HASH
2006-06-20 15:12:02 +04:00
help
2008-04-05 17:04:48 +04:00
Tiger hash algorithm 192, 160 and 128-bit hashes
2006-06-20 15:12:02 +04:00
2008-04-05 17:04:48 +04:00
Tiger is a hash function optimized for 64-bit processors while
still having decent performance on 32-bit processors.
Tiger was developed by Ross Anderson and Eli Biham.
2006-06-20 15:12:02 +04:00
See also:
2008-04-05 17:04:48 +04:00
<http://www.cs.technion.ac.il/~biham/Reports/Tiger/>.
2006-06-20 15:12:02 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_WP512
tristate "Whirlpool digest algorithms"
2008-12-07 14:34:37 +03:00
select CRYPTO_HASH
2005-04-17 02:20:36 +04:00
help
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Whirlpool hash algorithm 512, 384 and 256-bit hashes
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
Whirlpool-512 is part of the NESSIE cryptographic primitives.
Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard
2005-04-17 02:20:36 +04:00
See also:
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<http://planeta.terra.com.br/informatica/paulobarreto/WhirlpoolPage.html>
comment "Ciphers"
2005-04-17 02:20:36 +04:00
config CRYPTO_AES
tristate "AES cipher algorithms"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
AES cipher algorithms (FIPS-197). AES uses the Rijndael
2005-04-17 02:20:36 +04:00
algorithm.
Rijndael appears to be consistently a very good performer in
2008-04-05 17:04:48 +04:00
both hardware and software across a wide range of computing
environments regardless of its use in feedback or non-feedback
modes. Its key setup time is excellent, and its key agility is
good. Rijndael's very low memory requirements make it very well
suited for restricted-space environments, in which it also
demonstrates excellent performance. Rijndael's operations are
among the easiest to defend against power and timing attacks.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
The AES specifies three key sizes: 128, 192 and 256 bits
2005-04-17 02:20:36 +04:00
See <http://csrc.nist.gov/CryptoToolkit/aes/> for more information.
config CRYPTO_AES_586
tristate "AES cipher algorithms (i586)"
2006-08-21 15:08:13 +04:00
depends on (X86 || UML_X86) && !64BIT
select CRYPTO_ALGAPI
2007-11-10 14:07:16 +03:00
select CRYPTO_AES
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
AES cipher algorithms (FIPS-197). AES uses the Rijndael
2005-04-17 02:20:36 +04:00
algorithm.
Rijndael appears to be consistently a very good performer in
2008-04-05 17:04:48 +04:00
both hardware and software across a wide range of computing
environments regardless of its use in feedback or non-feedback
modes. Its key setup time is excellent, and its key agility is
good. Rijndael's very low memory requirements make it very well
suited for restricted-space environments, in which it also
demonstrates excellent performance. Rijndael's operations are
among the easiest to defend against power and timing attacks.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
The AES specifies three key sizes: 128, 192 and 256 bits
2005-07-07 00:55:00 +04:00
See <http://csrc.nist.gov/encryption/aes/> for more information.
config CRYPTO_AES_X86_64
tristate "AES cipher algorithms (x86_64)"
2006-08-21 15:08:13 +04:00
depends on (X86 || UML_X86) && 64BIT
select CRYPTO_ALGAPI
2007-11-08 16:25:04 +03:00
select CRYPTO_AES
2005-07-07 00:55:00 +04:00
help
2008-04-05 17:04:48 +04:00
AES cipher algorithms (FIPS-197). AES uses the Rijndael
2005-07-07 00:55:00 +04:00
algorithm.
Rijndael appears to be consistently a very good performer in
2008-04-05 17:04:48 +04:00
both hardware and software across a wide range of computing
environments regardless of its use in feedback or non-feedback
modes. Its key setup time is excellent, and its key agility is
2009-01-18 08:28:34 +03:00
good. Rijndael's very low memory requirements make it very well
suited for restricted-space environments, in which it also
demonstrates excellent performance. Rijndael's operations are
among the easiest to defend against power and timing attacks.
The AES specifies three key sizes: 128, 192 and 256 bits
See <http://csrc.nist.gov/encryption/aes/> for more information.
config CRYPTO_AES_NI_INTEL
tristate "AES cipher algorithms (AES-NI)"
depends on (X86 || UML_X86) && 64BIT
select CRYPTO_AES_X86_64
select CRYPTO_CRYPTD
select CRYPTO_ALGAPI
help
Use Intel AES-NI instructions for AES algorithm.
AES cipher algorithms (FIPS-197). AES uses the Rijndael
algorithm.
Rijndael appears to be consistently a very good performer in
both hardware and software across a wide range of computing
environments regardless of its use in feedback or non-feedback
modes. Its key setup time is excellent, and its key agility is
2008-04-05 17:04:48 +04:00
good. Rijndael's very low memory requirements make it very well
suited for restricted-space environments, in which it also
demonstrates excellent performance. Rijndael's operations are
among the easiest to defend against power and timing attacks.
2005-07-07 00:55:00 +04:00
2008-04-05 17:04:48 +04:00
The AES specifies three key sizes: 128, 192 and 256 bits
2005-04-17 02:20:36 +04:00
See <http://csrc.nist.gov/encryption/aes/> for more information.
2008-04-05 17:04:48 +04:00
config CRYPTO_ANUBIS
tristate "Anubis cipher algorithm"
select CRYPTO_ALGAPI
help
Anubis cipher algorithm.
Anubis is a variable key length cipher which can use keys from
128 bits to 320 bits in length. It was evaluated as a entrant
in the NESSIE competition.
See also:
<https://www.cosic.esat.kuleuven.ac.be/nessie/reports/>
<http://planeta.terra.com.br/informatica/paulobarreto/AnubisPage.html>
config CRYPTO_ARC4
tristate "ARC4 cipher algorithm"
select CRYPTO_ALGAPI
help
ARC4 cipher algorithm.
ARC4 is a stream cipher using keys ranging from 8 bits to 2048
bits in length. This algorithm is required for driver-based
WEP, but it should not be for other purposes because of the
weakness of the algorithm.
config CRYPTO_BLOWFISH
tristate "Blowfish cipher algorithm"
select CRYPTO_ALGAPI
help
Blowfish cipher algorithm, by Bruce Schneier.
This is a variable key length cipher which can use keys from 32
bits to 448 bits in length. It's fast, simple and specifically
designed for use on "large microprocessors".
See also:
<http://www.schneier.com/blowfish.html>
config CRYPTO_CAMELLIA
tristate "Camellia cipher algorithms"
depends on CRYPTO
select CRYPTO_ALGAPI
help
Camellia cipher algorithms module.
Camellia is a symmetric key block cipher developed jointly
at NTT and Mitsubishi Electric Corporation.
The Camellia specifies three key sizes: 128, 192 and 256 bits.
See also:
<https://info.isl.ntt.co.jp/crypt/eng/camellia/index_s.html>
2005-04-17 02:20:36 +04:00
config CRYPTO_CAST5
tristate "CAST5 (CAST-128) cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
The CAST5 encryption algorithm (synonymous with CAST-128) is
described in RFC2144.
config CRYPTO_CAST6
tristate "CAST6 (CAST-256) cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
The CAST6 encryption algorithm (synonymous with CAST-256) is
described in RFC2612.
2008-04-05 17:04:48 +04:00
config CRYPTO_DES
tristate "DES and Triple DES EDE cipher algorithms"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
2005-09-02 04:42:46 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_FCRYPT
tristate "FCrypt cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
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select CRYPTO_BLKCIPHER
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
FCrypt algorithm used by RxRPC.
2005-04-17 02:20:36 +04:00
config CRYPTO_KHAZAD
tristate "Khazad cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
Khazad cipher algorithm.
Khazad was a finalist in the initial NESSIE competition. It is
an algorithm optimized for 64-bit processors with good performance
on 32-bit processors. Khazad uses an 128 bit key size.
See also:
<http://planeta.terra.com.br/informatica/paulobarreto/KhazadPage.html>
2007-11-23 14:45:00 +03:00
config CRYPTO_SALSA20
tristate "Salsa20 stream cipher algorithm (EXPERIMENTAL)"
depends on EXPERIMENTAL
select CRYPTO_BLKCIPHER
help
Salsa20 stream cipher algorithm.
Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT
Stream Cipher Project. See <http://www.ecrypt.eu.org/stream/>
2007-12-10 10:52:56 +03:00
The Salsa20 stream cipher algorithm is designed by Daniel J.
Bernstein <djb@cr.yp.to>. See <http://cr.yp.to/snuffle.html>
config CRYPTO_SALSA20_586
tristate "Salsa20 stream cipher algorithm (i586) (EXPERIMENTAL)"
depends on (X86 || UML_X86) && !64BIT
depends on EXPERIMENTAL
select CRYPTO_BLKCIPHER
help
Salsa20 stream cipher algorithm.
Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT
Stream Cipher Project. See <http://www.ecrypt.eu.org/stream/>
2007-12-17 19:04:40 +03:00
The Salsa20 stream cipher algorithm is designed by Daniel J.
Bernstein <djb@cr.yp.to>. See <http://cr.yp.to/snuffle.html>
config CRYPTO_SALSA20_X86_64
tristate "Salsa20 stream cipher algorithm (x86_64) (EXPERIMENTAL)"
depends on (X86 || UML_X86) && 64BIT
depends on EXPERIMENTAL
select CRYPTO_BLKCIPHER
help
Salsa20 stream cipher algorithm.
Salsa20 is a stream cipher submitted to eSTREAM, the ECRYPT
Stream Cipher Project. See <http://www.ecrypt.eu.org/stream/>
2007-11-23 14:45:00 +03:00
The Salsa20 stream cipher algorithm is designed by Daniel J.
Bernstein <djb@cr.yp.to>. See <http://cr.yp.to/snuffle.html>
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_SEED
tristate "SEED cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
SEED cipher algorithm (RFC4269).
2005-04-17 02:20:36 +04:00
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SEED is a 128-bit symmetric key block cipher that has been
developed by KISA (Korea Information Security Agency) as a
national standard encryption algorithm of the Republic of Korea.
It is a 16 round block cipher with the key size of 128 bit.
See also:
<http://www.kisa.or.kr/kisa/seed/jsp/seed_eng.jsp>
config CRYPTO_SERPENT
tristate "Serpent cipher algorithm"
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select CRYPTO_ALGAPI
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help
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Serpent cipher algorithm, by Anderson, Biham & Knudsen.
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Keys are allowed to be from 0 to 256 bits in length, in steps
of 8 bits. Also includes the 'Tnepres' algorithm, a reversed
variant of Serpent for compatibility with old kerneli.org code.
See also:
<http://www.cl.cam.ac.uk/~rja14/serpent.html>
config CRYPTO_TEA
tristate "TEA, XTEA and XETA cipher algorithms"
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select CRYPTO_ALGAPI
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help
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TEA cipher algorithm.
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Tiny Encryption Algorithm is a simple cipher that uses
many rounds for security. It is very fast and uses
little memory.
Xtendend Tiny Encryption Algorithm is a modification to
the TEA algorithm to address a potential key weakness
in the TEA algorithm.
Xtendend Encryption Tiny Algorithm is a mis-implementation
of the XTEA algorithm for compatibility purposes.
config CRYPTO_TWOFISH
tristate "Twofish cipher algorithm"
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select CRYPTO_ALGAPI
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select CRYPTO_TWOFISH_COMMON
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help
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Twofish cipher algorithm.
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Twofish was submitted as an AES (Advanced Encryption Standard)
candidate cipher by researchers at CounterPane Systems. It is a
16 round block cipher supporting key sizes of 128, 192, and 256
bits.
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See also:
<http://www.schneier.com/twofish.html>
config CRYPTO_TWOFISH_COMMON
tristate
help
Common parts of the Twofish cipher algorithm shared by the
generic c and the assembler implementations.
config CRYPTO_TWOFISH_586
tristate "Twofish cipher algorithms (i586)"
depends on (X86 || UML_X86) && !64BIT
select CRYPTO_ALGAPI
select CRYPTO_TWOFISH_COMMON
help
Twofish cipher algorithm.
Twofish was submitted as an AES (Advanced Encryption Standard)
candidate cipher by researchers at CounterPane Systems. It is a
16 round block cipher supporting key sizes of 128, 192, and 256
bits.
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See also:
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<http://www.schneier.com/twofish.html>
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config CRYPTO_TWOFISH_X86_64
tristate "Twofish cipher algorithm (x86_64)"
depends on (X86 || UML_X86) && 64BIT
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select CRYPTO_ALGAPI
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select CRYPTO_TWOFISH_COMMON
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help
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Twofish cipher algorithm (x86_64).
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Twofish was submitted as an AES (Advanced Encryption Standard)
candidate cipher by researchers at CounterPane Systems. It is a
16 round block cipher supporting key sizes of 128, 192, and 256
bits.
See also:
<http://www.schneier.com/twofish.html>
comment "Compression"
config CRYPTO_DEFLATE
tristate "Deflate compression algorithm"
select CRYPTO_ALGAPI
select ZLIB_INFLATE
select ZLIB_DEFLATE
[CRYPTO] aead: Add authenc
This patch adds the authenc algorithm which constructs an AEAD algorithm
from an asynchronous block cipher and a hash. The construction is done
by concatenating the encrypted result from the cipher with the output
from the hash, as is used by the IPsec ESP protocol.
The authenc algorithm exists as a template with four parameters:
authenc(auth, authsize, enc, enckeylen).
The authentication algorithm, the authentication size (i.e., truncating
the output of the authentication algorithm), the encryption algorithm,
and the encryption key length. Both the size field and the key length
field are in bytes. For example, AES-128 with SHA1-HMAC would be
represented by
authenc(hmac(sha1), 12, cbc(aes), 16)
The key for the authenc algorithm is the concatenation of the keys for
the authentication algorithm with the encryption algorithm. For the
above example, if a key of length 36 bytes is given, then hmac(sha1)
would receive the first 20 bytes while the last 16 would be given to
cbc(aes).
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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help
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This is the Deflate algorithm (RFC1951), specified for use in
IPSec with the IPCOMP protocol (RFC3173, RFC2394).
You will most probably want this if using IPSec.
[CRYPTO] aead: Add authenc
This patch adds the authenc algorithm which constructs an AEAD algorithm
from an asynchronous block cipher and a hash. The construction is done
by concatenating the encrypted result from the cipher with the output
from the hash, as is used by the IPsec ESP protocol.
The authenc algorithm exists as a template with four parameters:
authenc(auth, authsize, enc, enckeylen).
The authentication algorithm, the authentication size (i.e., truncating
the output of the authentication algorithm), the encryption algorithm,
and the encryption key length. Both the size field and the key length
field are in bytes. For example, AES-128 with SHA1-HMAC would be
represented by
authenc(hmac(sha1), 12, cbc(aes), 16)
The key for the authenc algorithm is the concatenation of the keys for
the authentication algorithm with the encryption algorithm. For the
above example, if a key of length 36 bytes is given, then hmac(sha1)
would receive the first 20 bytes while the last 16 would be given to
cbc(aes).
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-08-30 12:24:15 +04:00
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config CRYPTO_LZO
tristate "LZO compression algorithm"
select CRYPTO_ALGAPI
select LZO_COMPRESS
select LZO_DECOMPRESS
help
This is the LZO algorithm.
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comment "Random Number Generation"
config CRYPTO_ANSI_CPRNG
tristate "Pseudo Random Number Generation for Cryptographic modules"
select CRYPTO_AES
select CRYPTO_RNG
select CRYPTO_FIPS
help
This option enables the generic pseudo random number generator
for cryptographic modules. Uses the Algorithm specified in
ANSI X9.31 A.2.4
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source "drivers/crypto/Kconfig"
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endif # if CRYPTO