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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/ *
* PowerPC v e r s i o n
* Copyright ( C ) 1 9 9 5 - 1 9 9 6 G a r y T h o m a s ( g d t @linuxppc.org)
* Rewritten b y C o r t D o u g a n ( c o r t @cs.nmt.edu) for PReP
* Copyright ( C ) 1 9 9 6 C o r t D o u g a n < c o r t @cs.nmt.edu>
* Low- l e v e l e x c e p t i o n h a n d l e r s a n d M M U s u p p o r t
* rewritten b y P a u l M a c k e r r a s .
* Copyright ( C ) 1 9 9 6 P a u l M a c k e r r a s .
* MPC8 x x m o d i f i c a t i o n s b y D a n M a l e k
* Copyright ( C ) 1 9 9 7 D a n M a l e k ( d m a l e k @jlc.net).
*
* This f i l e c o n t a i n s l o w - l e v e l s u p p o r t a n d s e t u p f o r P o w e r P C 8 x x
* embedded p r o c e s s o r s , i n c l u d i n g t r a p a n d i n t e r r u p t d i s p a t c h .
* /
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# include < l i n u x / i n i t . h >
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# include < l i n u x / m a g i c . h >
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# include < a s m / p r o c e s s o r . h >
# include < a s m / p a g e . h >
# include < a s m / m m u . h >
# include < a s m / c a c h e . h >
# include < a s m / p g t a b l e . h >
# include < a s m / c p u t a b l e . h >
# include < a s m / t h r e a d _ i n f o . h >
# include < a s m / p p c _ a s m . h >
# include < a s m / a s m - o f f s e t s . h >
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# include < a s m / p t r a c e . h >
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# include < a s m / e x p o r t . h >
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# include < a s m / c o d e - p a t c h i n g - a s m . h >
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# include " h e a d _ 3 2 . h "
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# if C O N F I G _ T A S K _ S I Z E < = 0 x80 0 0 0 0 0 0 & & C O N F I G _ P A G E _ O F F S E T > = 0 x80 0 0 0 0 0 0
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/* By simply checking Address >= 0x80000000, we know if its a kernel address */
# define S I M P L E _ K E R N E L _ A D D R E S S 1
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# endif
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/ *
* We n e e d a n I T L B m i s s h a n d l e r f o r k e r n e l a d d r e s s e s i f :
* - Either w e h a v e m o d u l e s
* - Or w e h a v e n o t p i n n e d t h e f i r s t 8 M
* /
# if d e f i n e d ( C O N F I G _ M O D U L E S ) | | ! d e f i n e d ( C O N F I G _ P I N _ T L B _ T E X T ) | | \
defined( C O N F I G _ D E B U G _ P A G E A L L O C )
# define I T L B _ M I S S _ K E R N E L 1
# endif
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/ *
* Value f o r t h e b i t s t h a t h a v e f i x e d v a l u e i n R P N e n t r i e s .
* Also u s e d f o r t a g g i n g D A R f o r D T L B e r r o r .
* /
# define R P N _ P A T T E R N 0 x00 f0
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# define P A G E _ S H I F T _ 5 1 2 K 1 9
# define P A G E _ S H I F T _ 8 M 2 3
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_ _ HEAD
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_ ENTRY( _ s t e x t ) ;
_ ENTRY( _ s t a r t ) ;
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/ * MPC8 x x
* This p o r t w a s d o n e o n a n M B X b o a r d w i t h a n 8 6 0 . R i g h t n o w I o n l y
* support a n E L F c o m p r e s s e d ( z I m a g e ) b o o t f r o m E P P C - B u g b e c a u s e t h e
* code t h e r e l o a d s u p s o m e r e g i s t e r s b e f o r e c a l l i n g u s :
* r3 : ptr t o b o a r d i n f o d a t a
* r4 : initrd_ s t a r t o r i f n o i n i t r d t h e n 0
* r5 : initrd_ e n d - u n u s e d i f r4 i s 0
* r6 : Start o f c o m m a n d l i n e s t r i n g
* r7 : End o f c o m m a n d l i n e s t r i n g
*
* I d e c i d e d t o u s e c o n d i t i o n a l c o m p i l a t i o n i n s t e a d o f c h e c k i n g P V R a n d
* adding m o r e p r o c e s s o r s p e c i f i c b r a n c h e s a r o u n d c o d e I d o n ' t n e e d .
* Since t h i s i s a n e m b e d d e d p r o c e s s o r , I a l s o a p p r e c i a t e a n y m e m o r y
* savings I c a n g e t .
*
* The M P C 8 x x d o e s n o t h a v e a n y B A T s , b u t i t s u p p o r t s l a r g e p a g e s i z e s .
* We f i r s t i n i t i a l i z e t h e M M U t o s u p p o r t 8 M b y t e p a g e s , t h e n l o a d o n e
* entry i n t o e a c h o f t h e i n s t r u c t i o n a n d d a t a T L B s t o m a p t h e f i r s t
* 8 M 1 : 1 . I a l s o m a p p e d a n a d d i t i o n a l I / O s p a c e 1 : 1 s o w e c a n g e t t o
* the " i n t e r n a l " p r o c e s s o r r e g i s t e r s b e f o r e M M U _ i n i t i s c a l l e d .
*
* - - Dan
* /
.globl __start
__start :
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mr r31 ,r3 / * s a v e d e v i c e t r e e p t r * /
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/ * We h a v e t o t u r n o n t h e M M U r i g h t a w a y s o w e g e t c a c h e m o d e s
* set c o r r e c t l y .
* /
bl i n i t i a l _ m m u
/ * We n o w h a v e t h e l o w e r 8 M e g m a p p e d i n t o T L B e n t r i e s , a n d t h e c a c h e s
* ready t o w o r k .
* /
turn_on_mmu :
mfmsr r0
ori r0 ,r0 ,M S R _ D R | M S R _ I R
mtspr S P R N _ S R R 1 ,r0
lis r0 ,s t a r t _ h e r e @h
ori r0 ,r0 ,s t a r t _ h e r e @l
mtspr S P R N _ S R R 0 ,r0
rfi / * e n a b l e s M M U * /
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# ifdef C O N F I G _ P E R F _ E V E N T S
.align 4
.globl itlb_miss_counter
itlb_miss_counter :
.space 4
.globl dtlb_miss_counter
dtlb_miss_counter :
.space 4
.globl instruction_counter
instruction_counter :
.space 4
# endif
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/* System reset */
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EXCEPTION( 0 x10 0 , R e s e t , s y s t e m _ r e s e t _ e x c e p t i o n , E X C _ X F E R _ S T D )
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/* Machine check */
. = 0 x2 0 0
MachineCheck :
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EXCEPTION_ P R O L O G h a n d l e _ d a r _ d s i s r =1
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save_ d a r _ d s i s r _ o n _ s t a c k r4 , r5 , r11
li r6 , R P N _ P A T T E R N
mtspr S P R N _ D A R , r6 / * T a g D A R , t o b e u s e d i n D T L B E r r o r * /
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addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
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EXC_ X F E R _ S T D ( 0 x20 0 , m a c h i n e _ c h e c k _ e x c e p t i o n )
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/* External interrupt */
EXCEPTION( 0 x50 0 , H a r d w a r e I n t e r r u p t , d o _ I R Q , E X C _ X F E R _ L I T E )
/* Alignment exception */
. = 0 x6 0 0
Alignment :
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EXCEPTION_ P R O L O G h a n d l e _ d a r _ d s i s r =1
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save_ d a r _ d s i s r _ o n _ s t a c k r4 , r5 , r11
li r6 , R P N _ P A T T E R N
mtspr S P R N _ D A R , r6 / * T a g D A R , t o b e u s e d i n D T L B E r r o r * /
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addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
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b . L a l i g n m e n t _ e x c e p t i o n _ o o l
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/* Program check exception */
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EXCEPTION( 0 x70 0 , P r o g r a m C h e c k , p r o g r a m _ c h e c k _ e x c e p t i o n , E X C _ X F E R _ S T D )
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/* Decrementer */
EXCEPTION( 0 x90 0 , D e c r e m e n t e r , t i m e r _ i n t e r r u p t , E X C _ X F E R _ L I T E )
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/* With VMAP_STACK there's not enough room for this at 0x600 */
. = 0 xa0 0
.Lalignment_exception_ool :
EXC_ X F E R _ S T D ( 0 x60 0 , a l i g n m e n t _ e x c e p t i o n )
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/* System call */
. = 0 xc0 0
SystemCall :
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SYSCALL_ E N T R Y 0 x c00
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/* Single step - not used on 601 */
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EXCEPTION( 0 x d00 , S i n g l e S t e p , s i n g l e _ s t e p _ e x c e p t i o n , E X C _ X F E R _ S T D )
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/ * On t h e M P C 8 x x , t h i s i s a s o f t w a r e e m u l a t i o n i n t e r r u p t . I t o c c u r s
* for a l l u n i m p l e m e n t e d a n d i l l e g a l i n s t r u c t i o n s .
* /
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EXCEPTION( 0 x10 0 0 , S o f t E m u , p r o g r a m _ c h e c k _ e x c e p t i o n , E X C _ X F E R _ S T D )
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. = 0 x1 1 0 0
/ *
* For t h e M P C 8 x x , t h i s i s a s o f t w a r e t a b l e w a l k t o l o a d t h e i n s t r u c t i o n
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* TLB. T h e t a s k s w i t c h l o a d s t h e M _ T W B r e g i s t e r w i t h t h e p o i n t e r t o t h e f i r s t
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* level t a b l e .
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* If w e d i s c o v e r t h e r e i s n o s e c o n d l e v e l t a b l e ( v a l u e i s z e r o ) o r i f t h e r e
* is a n i n v a l i d p t e , w e l o a d t h a t i n t o t h e T L B , w h i c h c a u s e s a n o t h e r f a u l t
* into t h e T L B E r r o r i n t e r r u p t w h e r e w e c a n h a n d l e s u c h p r o b l e m s .
* We h a v e t o u s e t h e M D _ x x x r e g i s t e r s f o r t h e t a b l e w a l k b e c a u s e t h e
* equivalent M I _ x x x r e g i s t e r s o n l y p e r f o r m t h e a t t r i b u t e f u n c t i o n s .
* /
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# ifdef C O N F I G _ 8 x x _ C P U 1 5
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# define I N V A L I D A T E _ A D J A C E N T _ P A G E S _ C P U 1 5 ( a d d r ) \
addi a d d r , a d d r , P A G E _ S I Z E ; \
tlbie a d d r ; \
addi a d d r , a d d r , - ( P A G E _ S I Z E < < 1 ) ; \
tlbie a d d r ; \
addi a d d r , a d d r , P A G E _ S I Z E
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# else
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# define I N V A L I D A T E _ A D J A C E N T _ P A G E S _ C P U 1 5 ( a d d r )
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# endif
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InstructionTLBMiss :
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mtspr S P R N _ S P R G _ S C R A T C H 0 , r10
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# if d e f i n e d ( I T L B _ M I S S _ K E R N E L ) | | d e f i n e d ( C O N F I G _ S W A P )
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mtspr S P R N _ S P R G _ S C R A T C H 1 , r11
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# endif
/ * If w e a r e f a u l t i n g a k e r n e l a d d r e s s , w e h a v e t o u s e t h e
* kernel p a g e t a b l e s .
* /
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mfspr r10 , S P R N _ S R R 0 / * G e t e f f e c t i v e a d d r e s s o f f a u l t * /
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INVALIDATE_ A D J A C E N T _ P A G E S _ C P U 1 5 ( r10 )
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mtspr S P R N _ M D _ E P N , r10
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/ * Only m o d u l e s w i l l c a u s e I T L B M i s s e s a s w e a l w a y s
* pin t h e f i r s t 8 M B o f k e r n e l m e m o r y * /
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# ifdef I T L B _ M I S S _ K E R N E L
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mfcr r11
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# if d e f i n e d ( S I M P L E _ K E R N E L _ A D D R E S S ) & & d e f i n e d ( C O N F I G _ P I N _ T L B _ T E X T )
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cmpi c r0 , r10 , 0 / * A d d r e s s > = 0 x80 0 0 0 0 0 0 * /
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# else
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rlwinm r10 , r10 , 1 6 , 0 x f f f8
cmpli c r0 , r10 , P A G E _ O F F S E T @h
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# ifndef C O N F I G _ P I N _ T L B _ T E X T
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/* It is assumed that kernel code fits into the first 32M */
0 : cmpli c r7 , r10 , ( P A G E _ O F F S E T + 0 x20 0 0 0 0 0 ) @h
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patch_ s i t e 0 b , p a t c h _ _ i t l b m i s s _ l i n m e m _ t o p
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# endif
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# endif
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# endif
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mfspr r10 , S P R N _ M _ T W B / * G e t l e v e l 1 t a b l e * /
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# ifdef I T L B _ M I S S _ K E R N E L
# if d e f i n e d ( S I M P L E _ K E R N E L _ A D D R E S S ) & & d e f i n e d ( C O N F I G _ P I N _ T L B _ T E X T )
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bge+ 3 f
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# else
blt+ 3 f
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# endif
# ifndef C O N F I G _ P I N _ T L B _ T E X T
blt c r7 , I T L B M i s s L i n e a r
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# endif
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rlwinm r10 , r10 , 0 , 2 0 , 3 1
oris r10 , r10 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @ha
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3 :
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# endif
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lwz r10 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @l(r10) /* Get level 1 entry */
mtspr S P R N _ M I _ T W C , r10 / * S e t s e g m e n t a t t r i b u t e s * /
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mtspr S P R N _ M D _ T W C , r10
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mfspr r10 , S P R N _ M D _ T W C
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lwz r10 , 0 ( r10 ) / * G e t t h e p t e * /
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# ifdef I T L B _ M I S S _ K E R N E L
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mtcr r11
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# endif
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# ifdef C O N F I G _ S W A P
rlwinm r11 , r10 , 3 2 - 5 , _ P A G E _ P R E S E N T
and r11 , r11 , r10
rlwimi r10 , r11 , 0 , _ P A G E _ P R E S E N T
# endif
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/ * The L i n u x P T E w o n ' t g o e x a c t l y i n t o t h e M M U T L B .
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* Software i n d i c a t o r b i t s 2 0 a n d 2 3 m u s t b e c l e a r .
* Software i n d i c a t o r b i t s 2 2 , 2 4 , 2 5 , 2 6 , a n d 2 7 m u s t b e
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* set. A l l o t h e r L i n u x P T E b i t s c o n t r o l t h e b e h a v i o r
* of t h e M M U .
* /
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rlwinm r10 , r10 , 0 , ~ 0 x0 f00 / * C l e a r b i t s 2 0 - 2 3 * /
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rlwimi r10 , r10 , 4 , 0 x04 0 0 / * C o p y _ P A G E _ E X E C i n t o b i t 2 1 * /
ori r10 , r10 , R P N _ P A T T E R N | 0 x20 0 / * S e t 2 2 a n d 2 4 - 2 7 * /
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mtspr S P R N _ M I _ R P N , r10 / * U p d a t e T L B e n t r y * /
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/* Restore registers */
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0 : mfspr r10 , S P R N _ S P R G _ S C R A T C H 0
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# if d e f i n e d ( I T L B _ M I S S _ K E R N E L ) | | d e f i n e d ( C O N F I G _ S W A P )
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mfspr r11 , S P R N _ S P R G _ S C R A T C H 1
# endif
rfi
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patch_ s i t e 0 b , p a t c h _ _ i t l b m i s s _ e x i t _ 1
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# ifdef C O N F I G _ P E R F _ E V E N T S
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patch_ s i t e 0 f , p a t c h _ _ i t l b m i s s _ p e r f
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0 : lwz r10 , ( i t l b _ m i s s _ c o u n t e r - P A G E _ O F F S E T ) @l(0)
addi r10 , r10 , 1
stw r10 , ( i t l b _ m i s s _ c o u n t e r - P A G E _ O F F S E T ) @l(0)
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mfspr r10 , S P R N _ S P R G _ S C R A T C H 0
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# if d e f i n e d ( I T L B _ M I S S _ K E R N E L ) | | d e f i n e d ( C O N F I G _ S W A P )
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mfspr r11 , S P R N _ S P R G _ S C R A T C H 1
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# endif
rfi
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# endif
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# ifndef C O N F I G _ P I N _ T L B _ T E X T
ITLBMissLinear :
mtcr r11
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# if d e f i n e d ( C O N F I G _ S T R I C T _ K E R N E L _ R W X ) & & C O N F I G _ E T E X T _ S H I F T < 2 3
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patch_ s i t e 0 f , p a t c h _ _ i t l b m i s s _ l i n m e m _ t o p8
mfspr r10 , S P R N _ S R R 0
0 : subis r11 , r10 , ( P A G E _ O F F S E T - 0 x80 0 0 0 0 0 0 ) @ha
rlwinm r11 , r11 , 4 , M I _ P S 8 M E G ^ M I _ P S 5 1 2 K
ori r11 , r11 , M I _ P S 5 1 2 K | M I _ S V A L I D
rlwinm r10 , r10 , 0 , 0 x0 f f80 0 0 0 / * 8 x x s u p p o r t s m a x 2 5 6 M b R A M * /
# else
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/* Set 8M byte page and mark it valid */
li r11 , M I _ P S 8 M E G | M I _ S V A L I D
rlwinm r10 , r10 , 2 0 , 0 x0 f80 0 0 0 0 / * 8 x x s u p p o r t s m a x 2 5 6 M b R A M * /
2019-02-21 22:08:51 +03:00
# endif
mtspr S P R N _ M I _ T W C , r11
2018-11-29 17:07:26 +03:00
ori r10 , r10 , 0 x f0 | M I _ S P S 1 6 K | _ P A G E _ S H | _ P A G E _ D I R T Y | \
_ PAGE_ P R E S E N T
mtspr S P R N _ M I _ R P N , r10 / * U p d a t e T L B e n t r y * /
0 : mfspr r10 , S P R N _ S P R G _ S C R A T C H 0
mfspr r11 , S P R N _ S P R G _ S C R A T C H 1
rfi
patch_ s i t e 0 b , p a t c h _ _ i t l b m i s s _ e x i t _ 2
# endif
2005-09-26 10:04:21 +04:00
. = 0 x1 2 0 0
DataStoreTLBMiss :
2019-12-21 11:32:31 +03:00
mtspr S P R N _ D A R , r10
mtspr S P R N _ M _ T W , r11
2018-11-29 17:07:24 +03:00
mfcr r11
2005-09-26 10:04:21 +04:00
/ * If w e a r e f a u l t i n g a k e r n e l a d d r e s s , w e h a v e t o u s e t h e
* kernel p a g e t a b l e s .
* /
2016-09-16 09:42:08 +03:00
mfspr r10 , S P R N _ M D _ E P N
2018-11-29 17:07:24 +03:00
rlwinm r10 , r10 , 1 6 , 0 x f f f8
cmpli c r0 , r10 , P A G E _ O F F S E T @h
2016-05-17 10:02:56 +03:00
# ifndef C O N F I G _ P I N _ T L B _ I M M R
2018-11-29 17:07:24 +03:00
cmpli c r6 , r10 , V I R T _ I M M R _ B A S E @h
2016-05-17 10:02:51 +03:00
# endif
2019-02-13 19:06:21 +03:00
0 : cmpli c r7 , r10 , ( P A G E _ O F F S E T + 0 x20 0 0 0 0 0 ) @h
2018-10-19 09:55:06 +03:00
patch_ s i t e 0 b , p a t c h _ _ d t l b m i s s _ l i n m e m _ t o p
2018-11-29 17:07:24 +03:00
mfspr r10 , S P R N _ M _ T W B / * G e t l e v e l 1 t a b l e * /
blt+ 3 f
2016-05-17 10:02:56 +03:00
# ifndef C O N F I G _ P I N _ T L B _ I M M R
2018-11-29 17:07:24 +03:00
0 : beq- c r6 , D T L B M i s s I M M R
2018-10-19 09:55:06 +03:00
patch_ s i t e 0 b , p a t c h _ _ d t l b m i s s _ i m m r _ j m p
2016-05-17 10:02:45 +03:00
# endif
2016-09-16 09:42:08 +03:00
blt c r7 , D T L B M i s s L i n e a r
2018-11-29 17:07:24 +03:00
rlwinm r10 , r10 , 0 , 2 0 , 3 1
oris r10 , r10 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @ha
2005-09-26 10:04:21 +04:00
3 :
2018-11-29 17:07:24 +03:00
mtcr r11
lwz r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @l(r10) /* Get level 1 entry */
2005-09-26 10:04:21 +04:00
2018-11-29 17:07:15 +03:00
mtspr S P R N _ M D _ T W C , r11
mfspr r10 , S P R N _ M D _ T W C
2005-09-26 10:04:21 +04:00
lwz r10 , 0 ( r10 ) / * G e t t h e p t e * /
2018-11-29 17:07:15 +03:00
2018-01-12 15:45:31 +03:00
/ * Insert t h e G u a r d e d f l a g i n t o t h e T W C f r o m t h e L i n u x P T E .
* It i s b i t 2 7 o f b o t h t h e L i n u x P T E a n d t h e T W C ( a t l e a s t
2005-09-26 10:04:21 +04:00
* I g o t t h a t r i g h t : - ) . I t w i l l b e b e t t e r w h e n w e c a n p u t
* this i n t o t h e L i n u x p g d / p m d a n d l o a d i t i n t h e o p e r a t i o n
* above.
* /
2018-01-12 15:45:31 +03:00
rlwimi r11 , r10 , 0 , _ P A G E _ G U A R D E D
2018-01-12 15:45:33 +03:00
mtspr S P R N _ M D _ T W C , r11
2018-10-19 09:54:54 +03:00
/ * Both _ P A G E _ A C C E S S E D a n d _ P A G E _ P R E S E N T h a s t o b e s e t .
* We a l s o n e e d t o k n o w i f t h e i n s n i s a l o a d / s t o r e , s o :
* Clear _ P A G E _ P R E S E N T a n d l o a d t h a t w h i c h w i l l
* trap i n t o D T L B E r r o r w i t h s t o r e b i t s e t a c c o r d i n l y .
* /
/ * PRESENT=0x1 , A C C E S S E D =0x20
* r1 1 = ( ( r10 & P R E S E N T ) & ( ( r10 & A C C E S S E D ) > > 5 ) ) ;
* r1 0 = ( r10 & ~ P R E S E N T ) | r11 ;
* /
# ifdef C O N F I G _ S W A P
rlwinm r11 , r10 , 3 2 - 5 , _ P A G E _ P R E S E N T
and r11 , r11 , r10
rlwimi r10 , r11 , 0 , _ P A G E _ P R E S E N T
# endif
2005-09-26 10:04:21 +04:00
/ * The L i n u x P T E w o n ' t g o e x a c t l y i n t o t h e M M U T L B .
* Software i n d i c a t o r b i t s 2 4 , 2 5 , 2 6 , a n d 2 7 m u s t b e
* set. A l l o t h e r L i n u x P T E b i t s c o n t r o l t h e b e h a v i o r
* of t h e M M U .
* /
2015-01-20 12:57:33 +03:00
li r11 , R P N _ P A T T E R N
2016-12-07 10:47:28 +03:00
rlwimi r10 , r11 , 0 , 2 4 , 2 7 / * S e t 2 4 - 2 7 * /
2018-01-12 15:45:19 +03:00
mtspr S P R N _ M D _ R P N , r10 / * U p d a t e T L B e n t r y * /
2005-09-26 10:04:21 +04:00
2010-03-02 08:37:12 +03:00
/* Restore registers */
2018-10-19 09:55:08 +03:00
2019-12-21 11:32:31 +03:00
0 : mfspr r10 , S P R N _ D A R
mtspr S P R N _ D A R , r11 / * T a g D A R * /
mfspr r11 , S P R N _ M _ T W
2018-01-12 15:45:23 +03:00
rfi
2018-10-19 09:55:08 +03:00
patch_ s i t e 0 b , p a t c h _ _ d t l b m i s s _ e x i t _ 1
2018-11-29 17:07:26 +03:00
DTLBMissIMMR :
mtcr r11
/* Set 512k byte guarded page and mark it valid */
li r10 , M D _ P S 5 1 2 K | M D _ G U A R D E D | M D _ S V A L I D
mtspr S P R N _ M D _ T W C , r10
mfspr r10 , S P R N _ I M M R / * G e t c u r r e n t I M M R * /
rlwinm r10 , r10 , 0 , 0 x f f f80 0 0 0 / * G e t 5 1 2 k b y t e s b o u n d a r y * /
ori r10 , r10 , 0 x f0 | M D _ S P S 1 6 K | _ P A G E _ S H | _ P A G E _ D I R T Y | \
_ PAGE_ P R E S E N T | _ P A G E _ N O _ C A C H E
mtspr S P R N _ M D _ R P N , r10 / * U p d a t e T L B e n t r y * /
li r11 , R P N _ P A T T E R N
2019-12-21 11:32:31 +03:00
0 : mfspr r10 , S P R N _ D A R
mtspr S P R N _ D A R , r11 / * T a g D A R * /
mfspr r11 , S P R N _ M _ T W
2018-11-29 17:07:26 +03:00
rfi
patch_ s i t e 0 b , p a t c h _ _ d t l b m i s s _ e x i t _ 2
DTLBMissLinear :
mtcr r11
2019-02-21 22:08:51 +03:00
rlwinm r10 , r10 , 2 0 , 0 x0 f80 0 0 0 0 / * 8 x x s u p p o r t s m a x 2 5 6 M b R A M * /
2019-02-21 22:08:52 +03:00
# if d e f i n e d ( C O N F I G _ S T R I C T _ K E R N E L _ R W X ) & & C O N F I G _ D A T A _ S H I F T < 2 3
2019-02-21 22:08:51 +03:00
patch_ s i t e 0 f , p a t c h _ _ d t l b m i s s _ r o m e m _ t o p8
0 : subis r11 , r10 , ( P A G E _ O F F S E T - 0 x80 0 0 0 0 0 0 ) @ha
rlwinm r11 , r11 , 0 , 0 x f f80 0 0 0 0
neg r10 , r11
or r11 , r11 , r10
rlwinm r11 , r11 , 4 , M I _ P S 8 M E G ^ M I _ P S 5 1 2 K
ori r11 , r11 , M I _ P S 5 1 2 K | M I _ S V A L I D
mfspr r10 , S P R N _ M D _ E P N
rlwinm r10 , r10 , 0 , 0 x0 f f80 0 0 0 / * 8 x x s u p p o r t s m a x 2 5 6 M b R A M * /
# else
2018-11-29 17:07:26 +03:00
/* Set 8M byte page and mark it valid */
li r11 , M D _ P S 8 M E G | M D _ S V A L I D
2019-02-21 22:08:51 +03:00
# endif
2018-11-29 17:07:26 +03:00
mtspr S P R N _ M D _ T W C , r11
2019-02-21 22:08:51 +03:00
# ifdef C O N F I G _ S T R I C T _ K E R N E L _ R W X
patch_ s i t e 0 f , p a t c h _ _ d t l b m i s s _ r o m e m _ t o p
0 : subis r11 , r10 , 0
rlwimi r10 , r11 , 1 1 , _ P A G E _ R O
# endif
2018-11-29 17:07:26 +03:00
ori r10 , r10 , 0 x f0 | M D _ S P S 1 6 K | _ P A G E _ S H | _ P A G E _ D I R T Y | \
_ PAGE_ P R E S E N T
mtspr S P R N _ M D _ R P N , r10 / * U p d a t e T L B e n t r y * /
li r11 , R P N _ P A T T E R N
2019-12-21 11:32:31 +03:00
0 : mfspr r10 , S P R N _ D A R
mtspr S P R N _ D A R , r11 / * T a g D A R * /
mfspr r11 , S P R N _ M _ T W
2018-11-29 17:07:26 +03:00
rfi
patch_ s i t e 0 b , p a t c h _ _ d t l b m i s s _ e x i t _ 3
2005-09-26 10:04:21 +04:00
/ * This i s a n i n s t r u c t i o n T L B e r r o r o n t h e M P C 8 x x . T h i s c o u l d b e d u e
* to m a n y r e a s o n s , s u c h a s e x e c u t i n g g u a r d e d m e m o r y o r i l l e g a l i n s t r u c t i o n
* addresses. T h e r e i s n o t h i n g t o d o b u t h a n d l e a b i g t i m e e r r o r f a u l t .
* /
. = 0 x1 3 0 0
InstructionTLBError :
2015-01-20 12:57:33 +03:00
EXCEPTION_ P R O L O G
2014-09-19 12:36:06 +04:00
mr r4 ,r12
2017-07-19 07:49:28 +03:00
andis. r5 ,r9 ,D S I S R _ S R R 1 _ M A T C H _ 3 2 S @h /* Filter relevant SRR1 bits */
andis. r10 ,r9 ,S R R 1 _ I S I _ N O P T @h
powerpc/8xx: hide itlbie and dtlbie symbols
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <itlbie>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0 <itlbie>:
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
For a cleaner code dump, this patch replaces itlbie and dtlbie
symbols by local symbols.
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <InstructionTLBError+0xa0>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-12-13 11:08:11 +03:00
beq+ . L i t l b i e
2014-09-19 12:36:10 +04:00
tlbie r4
2014-09-19 12:36:06 +04:00
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
powerpc/8xx: hide itlbie and dtlbie symbols
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <itlbie>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0 <itlbie>:
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
For a cleaner code dump, this patch replaces itlbie and dtlbie
symbols by local symbols.
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <InstructionTLBError+0xa0>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-12-13 11:08:11 +03:00
.Litlbie :
2019-12-21 11:32:24 +03:00
stw r4 , _ D A R ( r11 )
powerpc/8xx: hide itlbie and dtlbie symbols
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <itlbie>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0 <itlbie>:
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
For a cleaner code dump, this patch replaces itlbie and dtlbie
symbols by local symbols.
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <InstructionTLBError+0xa0>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-12-13 11:08:11 +03:00
EXC_ X F E R _ L I T E ( 0 x40 0 , h a n d l e _ p a g e _ f a u l t )
2005-09-26 10:04:21 +04:00
/ * This i s t h e d a t a T L B e r r o r o n t h e M P C 8 x x . T h i s c o u l d b e d u e t o
2014-08-29 13:14:38 +04:00
* many r e a s o n s , i n c l u d i n g a d i r t y u p d a t e t o a p t e . W e b a i l o u t t o
* a h i g h e r l e v e l f u n c t i o n t h a t c a n h a n d l e i t .
2005-09-26 10:04:21 +04:00
* /
. = 0 x1 4 0 0
DataTLBError :
2019-12-21 11:32:35 +03:00
EXCEPTION_ P R O L O G _ 0 h a n d l e _ d a r _ d s i s r =1
2014-08-29 13:14:38 +04:00
mfspr r11 , S P R N _ D A R
2019-12-21 11:32:25 +03:00
cmpwi c r1 , r11 , R P N _ P A T T E R N
beq- c r1 , F i x u p D A R / * m u s t b e a b u g g y d c b X , i c b i i n s n . * /
2014-08-29 13:14:37 +04:00
DARFixed : /* Return from dcbx instruction bug workaround */
2019-12-21 11:32:35 +03:00
# ifdef C O N F I G _ V M A P _ S T A C K
li r11 , R P N _ P A T T E R N
mtspr S P R N _ D A R , r11 / * T a g D A R , t o b e u s e d i n D T L B E r r o r * /
# endif
2014-09-19 12:36:08 +04:00
EXCEPTION_ P R O L O G _ 1
2019-12-21 11:32:35 +03:00
EXCEPTION_ P R O L O G _ 2 h a n d l e _ d a r _ d s i s r =1
2019-12-21 11:32:26 +03:00
get_ a n d _ s a v e _ d a r _ d s i s r _ o n _ s t a c k r4 , r5 , r11
2017-08-08 14:59:00 +03:00
andis. r10 ,r5 ,D S I S R _ N O H P T E @h
powerpc/8xx: hide itlbie and dtlbie symbols
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <itlbie>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0 <itlbie>:
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
For a cleaner code dump, this patch replaces itlbie and dtlbie
symbols by local symbols.
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <InstructionTLBError+0xa0>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-12-13 11:08:11 +03:00
beq+ . L d t l b i e
2014-09-19 12:36:10 +04:00
tlbie r4
powerpc/8xx: hide itlbie and dtlbie symbols
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <itlbie>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0 <itlbie>:
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
For a cleaner code dump, this patch replaces itlbie and dtlbie
symbols by local symbols.
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <InstructionTLBError+0xa0>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-12-13 11:08:11 +03:00
.Ldtlbie :
2019-12-21 11:32:35 +03:00
# ifndef C O N F I G _ V M A P _ S T A C K
powerpc/8xx: hide itlbie and dtlbie symbols
When disassembling InstructionTLBError we get the following messy code:
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <itlbie>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0 <itlbie>:
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
For a cleaner code dump, this patch replaces itlbie and dtlbie
symbols by local symbols.
c000138c: 7d 84 63 78 mr r4,r12
c0001390: 75 25 58 00 andis. r5,r9,22528
c0001394: 75 2a 40 00 andis. r10,r9,16384
c0001398: 41 a2 00 08 beq c00013a0 <InstructionTLBError+0xa0>
c000139c: 7c 00 22 64 tlbie r4,r0
c00013a0: 39 40 04 01 li r10,1025
c00013a4: 91 4b 00 b0 stw r10,176(r11)
c00013a8: 39 40 10 32 li r10,4146
c00013ac: 48 00 cc 59 bl c000e004 <transfer_to_handler>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-12-13 11:08:11 +03:00
li r10 ,R P N _ P A T T E R N
2014-09-19 12:36:07 +04:00
mtspr S P R N _ D A R ,r10 / * T a g D A R , t o b e u s e d i n D T L B E r r o r * /
2019-12-21 11:32:35 +03:00
# endif
2014-09-19 12:36:07 +04:00
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
EXC_ X F E R _ L I T E ( 0 x30 0 , h a n d l e _ p a g e _ f a u l t )
2005-09-26 10:04:21 +04:00
2019-12-21 11:32:33 +03:00
/* Called from DataStoreTLBMiss when perf TLB misses events are activated */
# ifdef C O N F I G _ P E R F _ E V E N T S
patch_ s i t e 0 f , p a t c h _ _ d t l b m i s s _ p e r f
0 : lwz r10 , ( d t l b _ m i s s _ c o u n t e r - P A G E _ O F F S E T ) @l(0)
addi r10 , r10 , 1
stw r10 , ( d t l b _ m i s s _ c o u n t e r - P A G E _ O F F S E T ) @l(0)
mfspr r10 , S P R N _ D A R
mtspr S P R N _ D A R , r11 / * T a g D A R * /
mfspr r11 , S P R N _ M _ T W
rfi
# endif
2019-12-21 11:32:35 +03:00
stack_overflow :
vmap_ s t a c k _ o v e r f l o w _ e x c e p t i o n
2005-09-26 10:04:21 +04:00
/ * On t h e M P C 8 x x , t h e s e n e x t f o u r t r a p s a r e u s e d f o r d e v e l o p m e n t
* support o f b r e a k p o i n t s a n d s u c h . S o m e d a y I w i l l g e t a r o u n d t o
* using t h e m .
* /
2019-12-21 11:32:34 +03:00
do_databreakpoint :
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
EXCEPTION_ P R O L O G _ 1
2019-12-21 11:32:35 +03:00
EXCEPTION_ P R O L O G _ 2 h a n d l e _ d a r _ d s i s r =1
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
addi r3 ,r1 ,S T A C K _ F R A M E _ O V E R H E A D
mfspr r4 ,S P R N _ B A R
stw r4 ,_ D A R ( r11 )
2019-12-21 11:32:35 +03:00
# ifdef C O N F I G _ V M A P _ S T A C K
lwz r5 ,_ D S I S R ( r11 )
# else
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
mfspr r5 ,S P R N _ D S I S R
2019-12-21 11:32:35 +03:00
# endif
2019-04-30 15:38:59 +03:00
EXC_ X F E R _ S T D ( 0 x1 c00 , d o _ b r e a k )
2019-12-21 11:32:34 +03:00
. = 0 x1 c00
DataBreakpoint :
2019-12-21 11:32:35 +03:00
EXCEPTION_ P R O L O G _ 0 h a n d l e _ d a r _ d s i s r =1
2019-12-21 11:32:34 +03:00
mfspr r11 , S P R N _ S R R 0
cmplwi c r1 , r11 , ( . L d t l b i e - P A G E _ O F F S E T ) @l
cmplwi c r7 , r11 , ( . L i t l b i e - P A G E _ O F F S E T ) @l
cror 4 * c r1 + e q , 4 * c r1 + e q , 4 * c r7 + e q
bne c r1 , d o _ d a t a b r e a k p o i n t
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
mtcr r10
2018-01-12 15:45:21 +03:00
mfspr r10 , S P R N _ S P R G _ S C R A T C H 0
mfspr r11 , S P R N _ S P R G _ S C R A T C H 1
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
rfi
2018-01-12 15:45:23 +03:00
# ifdef C O N F I G _ P E R F _ E V E N T S
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 15:42:18 +03:00
. = 0 x1 d00
InstructionBreakpoint :
2018-01-12 15:45:21 +03:00
mtspr S P R N _ S P R G _ S C R A T C H 0 , r10
2018-11-29 17:07:11 +03:00
lwz r10 , ( i n s t r u c t i o n _ c o u n t e r - P A G E _ O F F S E T ) @l(0)
addi r10 , r10 , - 1
stw r10 , ( i n s t r u c t i o n _ c o u n t e r - P A G E _ O F F S E T ) @l(0)
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 15:42:18 +03:00
lis r10 , 0 x f f f f
ori r10 , r10 , 0 x01
mtspr S P R N _ C O U N T A , r10
2018-01-12 15:45:21 +03:00
mfspr r10 , S P R N _ S P R G _ S C R A T C H 0
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 15:42:18 +03:00
rfi
# else
2019-04-30 15:38:59 +03:00
EXCEPTION( 0 x1 d00 , T r a p _ 1 d , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ S T D )
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 15:42:18 +03:00
# endif
2019-04-30 15:38:59 +03:00
EXCEPTION( 0 x1 e 0 0 , T r a p _ 1 e , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ S T D )
EXCEPTION( 0 x1 f00 , T r a p _ 1 f , u n k n o w n _ e x c e p t i o n , E X C _ X F E R _ S T D )
2005-09-26 10:04:21 +04:00
. = 0 x2 0 0 0
2009-11-20 03:21:06 +03:00
/ * This i s t h e p r o c e d u r e t o c a l c u l a t e t h e d a t a E A f o r b u g g y d c b x ,d c b i i n s t r u c t i o n s
* by d e c o d i n g t h e r e g i s t e r s u s e d b y t h e d c b x i n s t r u c t i o n a n d a d d i n g t h e m .
2014-08-29 13:14:37 +04:00
* DAR i s s e t t o t h e c a l c u l a t e d a d d r e s s .
2009-11-20 03:21:06 +03:00
* /
FixupDAR : /* Entry point for dcbx workaround. */
2018-11-29 17:07:24 +03:00
mtspr S P R N _ M _ T W , r10
2009-11-20 03:21:06 +03:00
/* fetch instruction from memory. */
mfspr r10 , S P R N _ S R R 0
2018-11-29 17:07:15 +03:00
mtspr S P R N _ M D _ E P N , r10
2017-07-12 13:08:47 +03:00
rlwinm r11 , r10 , 1 6 , 0 x f f f8
2019-12-21 11:32:25 +03:00
cmpli c r1 , r11 , P A G E _ O F F S E T @h
2018-11-29 17:07:15 +03:00
mfspr r11 , S P R N _ M _ T W B / * G e t l e v e l 1 t a b l e * /
2019-12-21 11:32:25 +03:00
blt+ c r1 , 3 f
2016-05-17 10:02:51 +03:00
rlwinm r11 , r10 , 1 6 , 0 x f f f8
2018-10-19 09:55:06 +03:00
0 : cmpli c r7 , r11 , ( P A G E _ O F F S E T + 0 x18 0 0 0 0 0 ) @h
patch_ s i t e 0 b , p a t c h _ _ f i x u p d a r _ l i n m e m _ t o p
2016-09-16 09:42:08 +03:00
/* create physical page address from effective address */
tophys( r11 , r10 )
blt- c r7 , 2 0 1 f
2018-11-29 17:07:15 +03:00
mfspr r11 , S P R N _ M _ T W B / * G e t l e v e l 1 t a b l e * /
rlwinm r11 , r11 , 0 , 2 0 , 3 1
oris r11 , r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @ha
3 :
2015-01-20 12:57:34 +03:00
lwz r11 , ( s w a p p e r _ p g _ d i r - P A G E _ O F F S E T ) @l(r11) /* Get the level 1 entry */
2018-11-29 17:07:15 +03:00
mtspr S P R N _ M D _ T W C , r11
2019-12-21 11:32:25 +03:00
mtcrf 0 x01 , r11
2018-11-29 17:07:15 +03:00
mfspr r11 , S P R N _ M D _ T W C
lwz r11 , 0 ( r11 ) / * G e t t h e p t e * /
2016-12-07 10:47:28 +03:00
bt 2 8 ,2 0 0 f / * b i t 2 8 = L a r g e p a g e ( 8 M ) * /
bt 2 9 ,2 0 2 f / * b i t 2 9 = L a r g e p a g e ( 8 M o r 5 1 2 K ) * /
2009-11-20 03:21:06 +03:00
/* concat physical page address(r11) and page offset(r10) */
2014-09-19 12:36:09 +04:00
rlwimi r11 , r10 , 0 , 3 2 - P A G E _ S H I F T , 3 1
powerpc/8xx: Map linear kernel RAM with 8M pages
On a live running system (VoIP gateway for Air Trafic Control), over
a 10 minutes period (with 277s idle), we get 87 millions DTLB misses
and approximatly 35 secondes are spent in DTLB handler.
This represents 5.8% of the overall time and even 10.8% of the
non-idle time.
Among those 87 millions DTLB misses, 15% are on user addresses and
85% are on kernel addresses. And within the kernel addresses, 93%
are on addresses from the linear address space and only 7% are on
addresses from the virtual address space.
MPC8xx has no BATs but it has 8Mb page size. This patch implements
mapping of kernel RAM using 8Mb pages, on the same model as what is
done on the 40x.
In 4k pages mode, each PGD entry maps a 4Mb area: we map every two
entries to the same 8Mb physical page. In each second entry, we add
4Mb to the page physical address to ease life of the FixupDAR
routine. This is just ignored by HW.
In 16k pages mode, each PGD entry maps a 64Mb area: each PGD entry
will point to the first page of the area. The DTLB handler adds
the 3 bits from EPN to map the correct page.
With this patch applied, we now get only 13 millions TLB misses
during the 10 minutes period. The idle time has increased to 313s
and the overall time spent in DTLB miss handler is 6.3s, which
represents 1% of the overall time and 2.2% of non-idle time.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-02-09 19:07:50 +03:00
201 : lwz r11 ,0 ( r11 )
2009-11-20 03:21:06 +03:00
/* Check if it really is a dcbx instruction. */
/ * dcbt a n d d c b t s t d o e s n o t g e n e r a t e D T L B M i s s e s / E r r o r s ,
* no n e e d t o i n c l u d e t h e m h e r e * /
2014-08-29 13:14:38 +04:00
xoris r10 , r11 , 0 x7 c00 / * c h e c k i f m a j o r O P c o d e i s 3 1 * /
rlwinm r10 , r10 , 0 , 2 1 , 5
2019-12-21 11:32:25 +03:00
cmpwi c r1 , r10 , 2 0 2 8 / * I s d c b z ? * /
beq+ c r1 , 1 4 2 f
cmpwi c r1 , r10 , 9 4 0 / * I s d c b i ? * /
beq+ c r1 , 1 4 2 f
cmpwi c r1 , r10 , 1 0 8 / * I s d c b s t ? * /
beq+ c r1 , 1 4 4 f / * F i x u p s t o r e b i t ! * /
cmpwi c r1 , r10 , 1 7 2 / * I s d c b f ? * /
beq+ c r1 , 1 4 2 f
cmpwi c r1 , r10 , 1 9 6 4 / * I s i c b i ? * /
beq+ c r1 , 1 4 2 f
2018-11-29 17:07:24 +03:00
141 : mfspr r10 ,S P R N _ M _ T W
2014-08-29 13:14:38 +04:00
b D A R F i x e d / * N o p e , g o b a c k t o n o r m a l T L B p r o c e s s i n g * /
2009-11-20 03:21:06 +03:00
2016-12-07 10:47:28 +03:00
200 :
/* concat physical page address(r11) and page offset(r10) */
rlwimi r11 , r10 , 0 , 3 2 - P A G E _ S H I F T _ 8 M , 3 1
b 2 0 1 b
202 :
/* concat physical page address(r11) and page offset(r10) */
rlwimi r11 , r10 , 0 , 3 2 - P A G E _ S H I F T _ 5 1 2 K , 3 1
b 2 0 1 b
2009-11-20 03:21:06 +03:00
144 : mfspr r10 , S P R N _ D S I S R
rlwinm r10 , r10 ,0 ,7 ,5 / * C l e a r s t o r e b i t f o r b u g g y d c b s t i n s n * /
mtspr S P R N _ D S I S R , r10
142 : /* continue, it was a dcbx, dcbi instruction. */
mfctr r10
mtdar r10 / * s a v e c t r r e g i n D A R * /
rlwinm r10 , r11 , 2 4 , 2 4 , 2 8 / * o f f s e t i n t o j u m p t a b l e f o r r e g R B * /
addi r10 , r10 , 1 5 0 f @l /* add start of table */
mtctr r10 / * l o a d c t r w i t h j u m p a d d r e s s * /
xor r10 , r10 , r10 / * s u m s t a r t s a t z e r o * /
bctr / * j u m p i n t o t a b l e * /
150 :
add r10 , r10 , r0 ;b 151f
add r10 , r10 , r1 ;b 151f
add r10 , r10 , r2 ;b 151f
add r10 , r10 , r3 ;b 151f
add r10 , r10 , r4 ;b 151f
add r10 , r10 , r5 ;b 151f
add r10 , r10 , r6 ;b 151f
add r10 , r10 , r7 ;b 151f
add r10 , r10 , r8 ;b 151f
add r10 , r10 , r9 ;b 151f
mtctr r11 ;b 154f /* r10 needs special handling */
mtctr r11 ;b 153f /* r11 needs special handling */
add r10 , r10 , r12 ;b 151f
add r10 , r10 , r13 ;b 151f
add r10 , r10 , r14 ;b 151f
add r10 , r10 , r15 ;b 151f
add r10 , r10 , r16 ;b 151f
add r10 , r10 , r17 ;b 151f
add r10 , r10 , r18 ;b 151f
add r10 , r10 , r19 ;b 151f
add r10 , r10 , r20 ;b 151f
add r10 , r10 , r21 ;b 151f
add r10 , r10 , r22 ;b 151f
add r10 , r10 , r23 ;b 151f
add r10 , r10 , r24 ;b 151f
add r10 , r10 , r25 ;b 151f
add r10 , r10 , r26 ;b 151f
add r10 , r10 , r27 ;b 151f
add r10 , r10 , r28 ;b 151f
add r10 , r10 , r29 ;b 151f
add r10 , r10 , r30 ;b 151f
add r10 , r10 , r31
151 :
2019-12-21 11:32:25 +03:00
rlwinm r11 ,r11 ,1 9 ,2 4 ,2 8 / * o f f s e t i n t o j u m p t a b l e f o r r e g R A * /
cmpwi c r1 , r11 , 0
beq c r1 , 1 5 2 f / * i f r e g R A i s z e r o , d o n ' t a d d i t * /
2009-11-20 03:21:06 +03:00
addi r11 , r11 , 1 5 0 b @l /* add start of table */
mtctr r11 / * l o a d c t r w i t h j u m p a d d r e s s * /
rlwinm r11 ,r11 ,0 ,1 6 ,1 0 / * m a k e s u r e w e d o n ' t e x e c u t e t h i s m o r e t h a n o n c e * /
bctr / * j u m p i n t o t a b l e * /
152 :
mfdar r11
mtctr r11 / * r e s t o r e c t r r e g f r o m D A R * /
2019-12-21 11:32:35 +03:00
# ifdef C O N F I G _ V M A P _ S T A C K
mfspr r11 , S P R N _ S P R G _ T H R E A D
stw r10 , D A R ( r11 )
mfspr r10 , S P R N _ D S I S R
stw r10 , D S I S R ( r11 )
# else
2009-11-20 03:21:06 +03:00
mtdar r10 / * s a v e f a u l t E A t o D A R * /
2019-12-21 11:32:35 +03:00
# endif
2018-11-29 17:07:24 +03:00
mfspr r10 ,S P R N _ M _ T W
2009-11-20 03:21:06 +03:00
b D A R F i x e d / * G o b a c k t o n o r m a l T L B h a n d l i n g * /
/* special handling for r10,r11 since these are modified already */
2014-08-29 13:14:37 +04:00
153 : mfspr r11 , S P R N _ S P R G _ S C R A T C H 1 / * l o a d r11 f r o m S P R N _ S P R G _ S C R A T C H 1 * /
2014-08-29 13:14:39 +04:00
add r10 , r10 , r11 / * a d d i t * /
mfctr r11 / * r e s t o r e r11 * /
b 1 5 1 b
2014-08-29 13:14:37 +04:00
154 : mfspr r11 , S P R N _ S P R G _ S C R A T C H 0 / * l o a d r10 f r o m S P R N _ S P R G _ S C R A T C H 0 * /
2014-08-29 13:14:39 +04:00
add r10 , r10 , r11 / * a d d i t * /
2009-11-20 03:21:06 +03:00
mfctr r11 / * r e s t o r e r11 * /
b 1 5 1 b
2005-09-26 10:04:21 +04:00
/ *
* This i s w h e r e t h e m a i n k e r n e l c o d e s t a r t s .
* /
start_here :
/* ptr to current */
lis r2 ,i n i t _ t a s k @h
ori r2 ,r2 ,i n i t _ t a s k @l
/* ptr to phys current thread */
tophys( r4 ,r2 )
addi r4 ,r4 ,T H R E A D / * i n i t t a s k ' s T H R E A D * /
2009-07-15 00:52:54 +04:00
mtspr S P R N _ S P R G _ T H R E A D ,r4
2005-09-26 10:04:21 +04:00
/* stack */
lis r1 ,i n i t _ t h r e a d _ u n i o n @ha
addi r1 ,r1 ,i n i t _ t h r e a d _ u n i o n @l
2019-08-21 13:20:51 +03:00
lis r0 , S T A C K _ E N D _ M A G I C @h
ori r0 , r0 , S T A C K _ E N D _ M A G I C @l
stw r0 , 0 ( r1 )
2005-09-26 10:04:21 +04:00
li r0 ,0
stwu r0 ,T H R E A D _ S I Z E - S T A C K _ F R A M E _ O V E R H E A D ( r1 )
2018-07-13 16:10:47 +03:00
lis r6 , s w a p p e r _ p g _ d i r @ha
tophys( r6 ,r6 )
2018-11-29 17:07:15 +03:00
mtspr S P R N _ M _ T W B , r6
2018-07-13 16:10:47 +03:00
2005-09-26 10:04:21 +04:00
bl e a r l y _ i n i t / * W e h a v e t o d o t h i s w i t h M M U o n * /
/ *
* Decide w h a t s o r t o f m a c h i n e t h i s i s a n d i n i t i a l i z e t h e M M U .
* /
2019-04-26 19:23:34 +03:00
# ifdef C O N F I G _ K A S A N
bl k a s a n _ e a r l y _ i n i t
# endif
2011-07-25 15:29:33 +04:00
li r3 ,0
mr r4 ,r31
2005-09-26 10:04:21 +04:00
bl m a c h i n e _ i n i t
bl M M U _ i n i t
/ *
* Go b a c k t o r u n n i n g u n m a p p e d s o w e c a n l o a d u p n e w v a l u e s
* and c h a n g e t o u s i n g o u r e x c e p t i o n v e c t o r s .
* On t h e 8 x x , a l l w e h a v e t o d o i s i n v a l i d a t e t h e T L B t o c l e a r
* the o l d 8 M b y t e T L B m a p p i n g s a n d l o a d t h e p a g e t a b l e b a s e r e g i s t e r .
* /
/ * The r i g h t w a y t o d o t h i s w o u l d b e t o t r a c k i t d o w n t h r o u g h
* init' s T H R E A D l i k e t h e c o n t e x t s w i t c h c o d e d o e s , b u t t h i s i s
* easier. . . . . . u n t i l s o m e o n e c h a n g e s i n i t ' s s t a t i c s t r u c t u r e s .
* /
lis r4 ,2 f @h
ori r4 ,r4 ,2 f @l
tophys( r4 ,r4 )
li r3 ,M S R _ K E R N E L & ~ ( M S R _ I R | M S R _ D R )
mtspr S P R N _ S R R 0 ,r4
mtspr S P R N _ S R R 1 ,r3
rfi
/* Load up the kernel context */
2 :
tlbia / * C l e a r a l l T L B e n t r i e s * /
sync / * w a i t f o r t l b i a / t l b i e t o f i n i s h * /
/ * set u p t h e P T E p o i n t e r s f o r t h e A b a t r o n b d i G D B .
* /
lis r5 , a b a t r o n _ p t e p t r s @h
ori r5 , r5 , a b a t r o n _ p t e p t r s @l
2018-05-24 14:02:06 +03:00
stw r5 , 0 x f0 ( 0 ) / * M u s t m a t c h y o u r A b a t r o n c o n f i g f i l e * /
2005-09-26 10:04:21 +04:00
tophys( r5 ,r5 )
2019-01-09 23:30:07 +03:00
lis r6 , s w a p p e r _ p g _ d i r @h
ori r6 , r6 , s w a p p e r _ p g _ d i r @l
2005-09-26 10:04:21 +04:00
stw r6 , 0 ( r5 )
/* Now turn on the MMU for real! */
li r4 ,M S R _ K E R N E L
lis r3 ,s t a r t _ k e r n e l @h
ori r3 ,r3 ,s t a r t _ k e r n e l @l
mtspr S P R N _ S R R 0 ,r3
mtspr S P R N _ S R R 1 ,r4
rfi / * e n a b l e M M U a n d j u m p t o s t a r t _ k e r n e l * /
/ * Set u p t h e i n i t i a l M M U s t a t e s o w e c a n d o t h e f i r s t l e v e l o f
* kernel i n i t i a l i z a t i o n . T h i s m a p s t h e f i r s t 8 M B y t e s o f m e m o r y 1 : 1
* virtual t o p h y s i c a l . A l s o , s e t t h e c a c h e m o d e s i n c e t h a t i s d e f i n e d
* by T L B e n t r i e s a n d p e r f o r m a n y a d d i t i o n a l m a p p i n g ( l i k e o f t h e I M M R ) .
* If c o n f i g u r e d t o p i n s o m e T L B s , w e p i n t h e f i r s t 8 M b y t e s o f k e r n e l ,
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 10:02:43 +03:00
* 2 4 Mbytes o f d a t a , a n d t h e 5 1 2 k I M M R s p a c e . A n y t h i n g n o t c o v e r e d b y
2005-09-26 10:04:21 +04:00
* these m a p p i n g s i s m a p p e d b y p a g e t a b l e s .
* /
initial_mmu :
2016-05-17 10:02:49 +03:00
li r8 , 0
mtspr S P R N _ M I _ C T R , r8 / * r e m o v e P I N N E D I T L B e n t r i e s * /
lis r10 , M D _ R E S E T V A L @h
# ifndef C O N F I G _ 8 x x _ C O P Y B A C K
oris r10 , r10 , M D _ W T D E F @h
# endif
mtspr S P R N _ M D _ C T R , r10 / * r e m o v e P I N N E D D T L B e n t r i e s * /
2005-09-26 10:04:21 +04:00
tlbia / * I n v a l i d a t e a l l T L B e n t r i e s * /
2017-07-12 13:08:51 +03:00
# ifdef C O N F I G _ P I N _ T L B _ D A T A
2016-05-17 10:02:49 +03:00
oris r10 , r10 , M D _ R S V 4 I @h
2005-09-26 10:04:21 +04:00
mtspr S P R N _ M D _ C T R , r10 / * S e t d a t a T L B c o n t r o l * /
2016-05-17 10:02:49 +03:00
# endif
2005-09-26 10:04:21 +04:00
2015-04-22 13:06:45 +03:00
lis r8 , M I _ A P G _ I N I T @h /* Set protection modes */
ori r8 , r8 , M I _ A P G _ I N I T @l
2005-09-26 10:04:21 +04:00
mtspr S P R N _ M I _ A P , r8
2015-04-22 13:06:45 +03:00
lis r8 , M D _ A P G _ I N I T @h
ori r8 , r8 , M D _ A P G _ I N I T @l
2005-09-26 10:04:21 +04:00
mtspr S P R N _ M D _ A P , r8
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 10:02:43 +03:00
/ * Map a 5 1 2 k p a g e f o r t h e I M M R t o g e t t h e p r o c e s s o r
2005-09-26 10:04:21 +04:00
* internal r e g i s t e r s ( a m o n g o t h e r t h i n g s ) .
* /
2016-05-17 10:02:56 +03:00
# ifdef C O N F I G _ P I N _ T L B _ I M M R
2017-07-12 13:08:51 +03:00
oris r10 , r10 , M D _ R S V 4 I @h
2016-05-17 10:02:56 +03:00
ori r10 , r10 , 0 x1 c00
mtspr S P R N _ M D _ C T R , r10
2005-09-26 10:04:21 +04:00
mfspr r9 , 6 3 8 / * G e t c u r r e n t I M M R * /
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 10:02:43 +03:00
andis. r9 , r9 , 0 x f f f8 / * G e t 5 1 2 k b y t e s b o u n d a r y * /
2005-09-26 10:04:21 +04:00
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 10:02:43 +03:00
lis r8 , V I R T _ I M M R _ B A S E @h /* Create vaddr for TLB */
2005-09-26 10:04:21 +04:00
ori r8 , r8 , M D _ E V A L I D / * M a r k i t v a l i d * /
mtspr S P R N _ M D _ E P N , r8
powerpc/8xx: Fix vaddr for IMMR early remap
Memory: 124428K/131072K available (3748K kernel code, 188K rwdata,
648K rodata, 508K init, 290K bss, 6644K reserved)
Kernel virtual memory layout:
* 0xfffdf000..0xfffff000 : fixmap
* 0xfde00000..0xfe000000 : consistent mem
* 0xfddf6000..0xfde00000 : early ioremap
* 0xc9000000..0xfddf6000 : vmalloc & ioremap
SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Today, IMMR is mapped 1:1 at startup
Mapping IMMR 1:1 is just wrong because it may overlap with another
area. On most mpc8xx boards it is OK as IMMR is set to 0xff000000
but for instance on EP88xC board, IMMR is at 0xfa200000 which
overlaps with VM ioremap area
This patch fixes the virtual address for remapping IMMR with the fixmap
regardless of the value of IMMR.
The size of IMMR area is 256kbytes (CPM at offset 0, security engine
at offset 128k) so a 512k page is enough
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-05-17 10:02:43 +03:00
li r8 , M D _ P S 5 1 2 K | M D _ G U A R D E D / * S e t 5 1 2 k b y t e p a g e * /
2018-10-19 09:54:54 +03:00
ori r8 , r8 , M D _ S V A L I D / * M a k e i t v a l i d * /
2005-09-26 10:04:21 +04:00
mtspr S P R N _ M D _ T W C , r8
mr r8 , r9 / * C r e a t e p a d d r f o r T L B * /
ori r8 , r8 , M I _ B O O T I N I T | 0 x2 / * I n h i b i t c a c h e - - C o r t * /
mtspr S P R N _ M D _ R P N , r8
# endif
2019-02-13 19:06:21 +03:00
/* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
# ifdef C O N F I G _ P I N _ T L B _ T E X T
lis r8 , M I _ R S V 4 I @h
ori r8 , r8 , 0 x1 c00
# endif
li r9 , 4 / * u p t o 4 p a g e s o f 8 M * /
mtctr r9
lis r9 , K E R N E L B A S E @h /* Create vaddr for TLB */
li r10 , M I _ P S 8 M E G | M I _ S V A L I D / * S e t 8 M b y t e p a g e * /
li r11 , M I _ B O O T I N I T / * C r e a t e R P N f o r a d d r e s s 0 * /
lis r12 , _ e i n i t t e x t @h
ori r12 , r12 , _ e i n i t t e x t @l
1 :
# ifdef C O N F I G _ P I N _ T L B _ T E X T
mtspr S P R N _ M I _ C T R , r8 / * S e t i n s t r u c t i o n M M U c o n t r o l * /
addi r8 , r8 , 0 x10 0
# endif
ori r0 , r9 , M I _ E V A L I D / * M a r k i t v a l i d * /
mtspr S P R N _ M I _ E P N , r0
mtspr S P R N _ M I _ T W C , r10
mtspr S P R N _ M I _ R P N , r11 / * S t o r e T L B e n t r y * /
addis r9 , r9 , 0 x80
addis r11 , r11 , 0 x80
cmpl c r0 , r9 , r12
bdnzf g t , 1 b
2005-09-26 10:04:21 +04:00
/ * Since t h e c a c h e i s e n a b l e d a c c o r d i n g t o t h e i n f o r m a t i o n w e
* just l o a d e d i n t o t h e T L B , i n v a l i d a t e a n d e n a b l e t h e c a c h e s h e r e .
* We s h o u l d p r o b a b l y c h e c k / s e t o t h e r m o d e s . . . . l a t e r .
* /
lis r8 , I D C _ I N V A L L @h
mtspr S P R N _ I C _ C S T , r8
mtspr S P R N _ D C _ C S T , r8
lis r8 , I D C _ E N A B L E @h
mtspr S P R N _ I C _ C S T , r8
# ifdef C O N F I G _ 8 x x _ C O P Y B A C K
mtspr S P R N _ D C _ C S T , r8
# else
/ * For a d e b u g o p t i o n , I l e f t t h i s h e r e t o e a s i l y e n a b l e
* the w r i t e t h r o u g h c a c h e m o d e
* /
lis r8 , D C _ S F W T @h
mtspr S P R N _ D C _ C S T , r8
lis r8 , I D C _ E N A B L E @h
mtspr S P R N _ D C _ C S T , r8
# endif
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 15:42:18 +03:00
/* Disable debug mode entry on breakpoints */
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
mfspr r8 , S P R N _ D E R
2018-01-12 15:45:23 +03:00
# ifdef C O N F I G _ P E R F _ E V E N T S
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 15:42:18 +03:00
rlwinm r8 , r8 , 0 , ~ 0 x c
# else
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
rlwinm r8 , r8 , 0 , ~ 0 x8
powerpc/8xx: Perf events on PPC 8xx
This patch has been reworked since RFC version. In the RFC, this patch
was preceded by a patch clearing MSR RI for all PPC32 at all time at
exception prologs. Now MSR RI clearing is done only when this 8xx perf
events functionality is compiled in, it is therefore limited to 8xx
and merged inside this patch.
Other main changes have been to take into account detailed review from
Peter Zijlstra. The instructions counter has been reworked to behave
as a free running counter like the three other counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following events (as reported by 'perf list'):
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses [Hardware cache event]
iTLB-load-misses [Hardware cache event]
'cycles' event is implemented using the timebase clock. Timebase clock
corresponds to CPU clock divided by 16, so number of cycles is
approximatly 16 times the number of TB ticks
On the 8xx, TLB misses are handled by software. It is therefore
easy to count all TLB misses each time the TLB miss exception is
called.
'instructions' is calculated by using instruction watchpoint counter.
This patch sets counter A to count instructions at address greater
than 0, hence we count all instructions executed while MSR RI bit is
set. The counter is set to the maximum which is 0xffff. Every 65535
instructions, debug instruction breakpoint exception fires. The
exception handler increments a counter in memory which then
represent the upper part of the instruction counter. We therefore
end up with a 48 bits counter. In order to avoid unnecessary overhead
while no perf event is active, this counter is started when the first
event referring to this counter is added, and the counter is stopped
when the last event referring to it is deleted. In order to properly
support breakpoint exceptions, MSR RI bit has to be unset in exception
epilogs in order to avoid breakpoint exceptions during critical
sections during changes to SRR0 and SRR1 would be problematic.
All counters are handled as free running counters.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-12-15 15:42:18 +03:00
# endif
powerpc/8xx: Implement hw_breakpoint
This patch implements HW breakpoint on the 8xx. The 8xx has
capability to manage HW breakpoints, which is slightly different
than BOOK3S:
1/ The breakpoint match doesn't trigger a DSI exception but a
dedicated data breakpoint exception.
2/ The breakpoint happens after the instruction has completed,
no need to single step or emulate the instruction,
3/ Matched address is not set in DAR but in BAR,
4/ DABR register doesn't exist, instead we have registers
LCTRL1, LCTRL2 and CMPx registers,
5/ The match on one comparator is not on a double word but
on a single word.
The patch does:
1/ Prepare the dedicated registers in call to __set_dabr(). In order
to emulate the double word handling of BOOK3S, comparator E is set to
DABR address value and comparator F to address + 4. Then breakpoint 1
is set to match comparator E or F,
2/ Skip the singlestepping stage when compiled for CONFIG_PPC_8xx,
3/ Implement the exception. In that exception, the matched address
is taken from SPRN_BAR and manage as if it was from SPRN_DAR.
4/ I/D TLB error exception routines perform a tlbie on bad TLBs. That
tlbie triggers the breakpoint exception when performed on the
breakpoint address. For this reason, the routine returns if the match
is from one of those two tlbie.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-11-29 11:52:15 +03:00
mtspr S P R N _ D E R , r8
2005-09-26 10:04:21 +04:00
blr
/ *
* We p u t a f e w t h i n g s h e r e t h a t h a v e t o b e p a g e - a l i g n e d .
* This s t u f f g o e s a t t h e b e g i n n i n g o f t h e d a t a s e g m e n t ,
* which i s p a g e - a l i g n e d .
* /
.data
.globl sdata
sdata :
.globl empty_zero_page
2014-09-19 12:36:09 +04:00
.align PAGE_SHIFT
2005-09-26 10:04:21 +04:00
empty_zero_page :
2014-09-19 12:36:09 +04:00
.space PAGE_SIZE
2016-01-14 07:33:46 +03:00
EXPORT_ S Y M B O L ( e m p t y _ z e r o _ p a g e )
2005-09-26 10:04:21 +04:00
.globl swapper_pg_dir
swapper_pg_dir :
2014-09-19 12:36:09 +04:00
.space PGD_TABLE_SIZE
2005-09-26 10:04:21 +04:00
/ * Room f o r t w o P T E t a b l e p o i n e r s , u s u a l l y t h e k e r n e l a n d c u r r e n t u s e r
* pointer t o t h e i r r e s p e c t i v e r o o t p a g e t a b l e ( p g d i r ) .
* /
2019-02-21 13:37:53 +03:00
.globl abatron_pteptrs
2005-09-26 10:04:21 +04:00
abatron_pteptrs :
.space 8
