License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 17:07:57 +03:00
/* SPDX-License-Identifier: GPL-2.0 */
2007-12-14 04:35:10 +03:00
# ifndef __KVM_X86_MMU_H
# define __KVM_X86_MMU_H
2007-12-16 12:02:48 +03:00
# include <linux/kvm_host.h>
2009-12-07 13:16:48 +03:00
# include "kvm_cache_regs.h"
2020-07-10 18:48:03 +03:00
# include "cpuid.h"
2007-12-14 04:35:10 +03:00
2022-08-04 01:49:57 +03:00
extern bool __read_mostly enable_mmio_caching ;
2008-04-25 06:17:08 +04:00
# define PT_WRITABLE_SHIFT 1
2016-03-22 11:51:20 +03:00
# define PT_USER_SHIFT 2
2008-04-25 06:17:08 +04:00
# define PT_PRESENT_MASK (1ULL << 0)
# define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
2016-03-22 11:51:20 +03:00
# define PT_USER_MASK (1ULL << PT_USER_SHIFT)
2008-04-25 06:17:08 +04:00
# define PT_PWT_MASK (1ULL << 3)
# define PT_PCD_MASK (1ULL << 4)
2008-05-15 14:51:35 +04:00
# define PT_ACCESSED_SHIFT 5
# define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
2012-09-12 14:44:53 +04:00
# define PT_DIRTY_SHIFT 6
# define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
2012-09-12 21:46:56 +04:00
# define PT_PAGE_SIZE_SHIFT 7
# define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
2008-04-25 06:17:08 +04:00
# define PT_PAT_MASK (1ULL << 7)
# define PT_GLOBAL_MASK (1ULL << 8)
# define PT64_NX_SHIFT 63
# define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
# define PT_PAT_SHIFT 7
# define PT_DIR_PAT_SHIFT 12
# define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
2017-08-24 15:27:55 +03:00
# define PT64_ROOT_5LEVEL 5
2017-08-24 15:27:54 +03:00
# define PT64_ROOT_4LEVEL 4
2008-04-25 06:17:08 +04:00
# define PT32_ROOT_LEVEL 2
# define PT32E_ROOT_LEVEL 3
2021-09-19 05:42:46 +03:00
# define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE )
2021-06-22 20:57:02 +03:00
# define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
2022-02-09 12:56:05 +03:00
# define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
2021-06-22 20:57:02 +03:00
2021-01-13 23:45:15 +03:00
static __always_inline u64 rsvd_bits ( int s , int e )
2014-09-01 14:44:04 +04:00
{
2021-01-13 23:45:15 +03:00
BUILD_BUG_ON ( __builtin_constant_p ( e ) & & __builtin_constant_p ( s ) & & e < s ) ;
if ( __builtin_constant_p ( e ) )
BUILD_BUG_ON ( e > 63 ) ;
else
e & = 63 ;
2017-08-24 15:27:53 +03:00
if ( e < s )
return 0 ;
2020-12-22 13:20:43 +03:00
return ( ( 2ULL < < ( e - s ) ) - 1 ) < < s ;
2014-09-01 14:44:04 +04:00
}
KVM: x86/mmu: Do not create SPTEs for GFNs that exceed host.MAXPHYADDR
Disallow memslots and MMIO SPTEs whose gpa range would exceed the host's
MAXPHYADDR, i.e. don't create SPTEs for gfns that exceed host.MAXPHYADDR.
The TDP MMU bounds its zapping based on host.MAXPHYADDR, and so if the
guest, possibly with help from userspace, manages to coerce KVM into
creating a SPTE for an "impossible" gfn, KVM will leak the associated
shadow pages (page tables):
WARNING: CPU: 10 PID: 1122 at arch/x86/kvm/mmu/tdp_mmu.c:57
kvm_mmu_uninit_tdp_mmu+0x4b/0x60 [kvm]
Modules linked in: kvm_intel kvm irqbypass
CPU: 10 PID: 1122 Comm: set_memory_regi Tainted: G W 5.18.0-rc1+ #293
Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015
RIP: 0010:kvm_mmu_uninit_tdp_mmu+0x4b/0x60 [kvm]
Call Trace:
<TASK>
kvm_arch_destroy_vm+0x130/0x1b0 [kvm]
kvm_destroy_vm+0x162/0x2d0 [kvm]
kvm_vm_release+0x1d/0x30 [kvm]
__fput+0x82/0x240
task_work_run+0x5b/0x90
exit_to_user_mode_prepare+0xd2/0xe0
syscall_exit_to_user_mode+0x1d/0x40
entry_SYSCALL_64_after_hwframe+0x44/0xae
</TASK>
On bare metal, encountering an impossible gpa in the page fault path is
well and truly impossible, barring CPU bugs, as the CPU will signal #PF
during the gva=>gpa translation (or a similar failure when stuffing a
physical address into e.g. the VMCS/VMCB). But if KVM is running as a VM
itself, the MAXPHYADDR enumerated to KVM may not be the actual MAXPHYADDR
of the underlying hardware, in which case the hardware will not fault on
the illegal-from-KVM's-perspective gpa.
Alternatively, KVM could continue allowing the dodgy behavior and simply
zap the max possible range. But, for hosts with MAXPHYADDR < 52, that's
a (minor) waste of cycles, and more importantly, KVM can't reasonably
support impossible memslots when running on bare metal (or with an
accurate MAXPHYADDR as a VM). Note, limiting the overhead by checking if
KVM is running as a guest is not a safe option as the host isn't required
to announce itself to the guest in any way, e.g. doesn't need to set the
HYPERVISOR CPUID bit.
A second alternative to disallowing the memslot behavior would be to
disallow creating a VM with guest.MAXPHYADDR > host.MAXPHYADDR. That
restriction is undesirable as there are legitimate use cases for doing
so, e.g. using the highest host.MAXPHYADDR out of a pool of heterogeneous
systems so that VMs can be migrated between hosts with different
MAXPHYADDRs without running afoul of the allow_smaller_maxphyaddr mess.
Note that any guest.MAXPHYADDR is valid with shadow paging, and it is
even useful in order to test KVM with MAXPHYADDR=52 (i.e. without
any reserved physical address bits).
The now common kvm_mmu_max_gfn() is inclusive instead of exclusive.
The memslot and TDP MMU code want an exclusive value, but the name
implies the returned value is inclusive, and the MMIO path needs an
inclusive check.
Fixes: faaf05b00aec ("kvm: x86/mmu: Support zapping SPTEs in the TDP MMU")
Fixes: 524a1e4e381f ("KVM: x86/mmu: Don't leak non-leaf SPTEs when zapping all SPTEs")
Cc: stable@vger.kernel.org
Cc: Maxim Levitsky <mlevitsk@redhat.com>
Cc: Ben Gardon <bgardon@google.com>
Cc: David Matlack <dmatlack@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220428233416.2446833-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-29 02:34:16 +03:00
static inline gfn_t kvm_mmu_max_gfn ( void )
{
/*
* Note that this uses the host MAXPHYADDR , not the guest ' s .
* EPT / NPT cannot support GPAs that would exceed host . MAXPHYADDR ;
* assuming KVM is running on bare metal , guest accesses beyond
* host . MAXPHYADDR will hit a # PF ( RSVD ) and never cause a vmexit
* ( either EPT Violation / Misconfig or # NPF ) , and so KVM will never
* install a SPTE for such addresses . If KVM is running as a VM
* itself , on the other hand , it might see a MAXPHYADDR that is less
* than hardware ' s real MAXPHYADDR . Using the host MAXPHYADDR
* disallows such SPTEs entirely and simplifies the TDP MMU .
*/
2024-04-24 01:15:21 +03:00
int max_gpa_bits = likely ( tdp_enabled ) ? kvm_host . maxphyaddr : 52 ;
KVM: x86/mmu: Do not create SPTEs for GFNs that exceed host.MAXPHYADDR
Disallow memslots and MMIO SPTEs whose gpa range would exceed the host's
MAXPHYADDR, i.e. don't create SPTEs for gfns that exceed host.MAXPHYADDR.
The TDP MMU bounds its zapping based on host.MAXPHYADDR, and so if the
guest, possibly with help from userspace, manages to coerce KVM into
creating a SPTE for an "impossible" gfn, KVM will leak the associated
shadow pages (page tables):
WARNING: CPU: 10 PID: 1122 at arch/x86/kvm/mmu/tdp_mmu.c:57
kvm_mmu_uninit_tdp_mmu+0x4b/0x60 [kvm]
Modules linked in: kvm_intel kvm irqbypass
CPU: 10 PID: 1122 Comm: set_memory_regi Tainted: G W 5.18.0-rc1+ #293
Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 0.0.0 02/06/2015
RIP: 0010:kvm_mmu_uninit_tdp_mmu+0x4b/0x60 [kvm]
Call Trace:
<TASK>
kvm_arch_destroy_vm+0x130/0x1b0 [kvm]
kvm_destroy_vm+0x162/0x2d0 [kvm]
kvm_vm_release+0x1d/0x30 [kvm]
__fput+0x82/0x240
task_work_run+0x5b/0x90
exit_to_user_mode_prepare+0xd2/0xe0
syscall_exit_to_user_mode+0x1d/0x40
entry_SYSCALL_64_after_hwframe+0x44/0xae
</TASK>
On bare metal, encountering an impossible gpa in the page fault path is
well and truly impossible, barring CPU bugs, as the CPU will signal #PF
during the gva=>gpa translation (or a similar failure when stuffing a
physical address into e.g. the VMCS/VMCB). But if KVM is running as a VM
itself, the MAXPHYADDR enumerated to KVM may not be the actual MAXPHYADDR
of the underlying hardware, in which case the hardware will not fault on
the illegal-from-KVM's-perspective gpa.
Alternatively, KVM could continue allowing the dodgy behavior and simply
zap the max possible range. But, for hosts with MAXPHYADDR < 52, that's
a (minor) waste of cycles, and more importantly, KVM can't reasonably
support impossible memslots when running on bare metal (or with an
accurate MAXPHYADDR as a VM). Note, limiting the overhead by checking if
KVM is running as a guest is not a safe option as the host isn't required
to announce itself to the guest in any way, e.g. doesn't need to set the
HYPERVISOR CPUID bit.
A second alternative to disallowing the memslot behavior would be to
disallow creating a VM with guest.MAXPHYADDR > host.MAXPHYADDR. That
restriction is undesirable as there are legitimate use cases for doing
so, e.g. using the highest host.MAXPHYADDR out of a pool of heterogeneous
systems so that VMs can be migrated between hosts with different
MAXPHYADDRs without running afoul of the allow_smaller_maxphyaddr mess.
Note that any guest.MAXPHYADDR is valid with shadow paging, and it is
even useful in order to test KVM with MAXPHYADDR=52 (i.e. without
any reserved physical address bits).
The now common kvm_mmu_max_gfn() is inclusive instead of exclusive.
The memslot and TDP MMU code want an exclusive value, but the name
implies the returned value is inclusive, and the MMIO path needs an
inclusive check.
Fixes: faaf05b00aec ("kvm: x86/mmu: Support zapping SPTEs in the TDP MMU")
Fixes: 524a1e4e381f ("KVM: x86/mmu: Don't leak non-leaf SPTEs when zapping all SPTEs")
Cc: stable@vger.kernel.org
Cc: Maxim Levitsky <mlevitsk@redhat.com>
Cc: Ben Gardon <bgardon@google.com>
Cc: David Matlack <dmatlack@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20220428233416.2446833-1-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-29 02:34:16 +03:00
return ( 1ULL < < ( max_gpa_bits - PAGE_SHIFT ) ) - 1 ;
}
2024-03-13 15:58:43 +03:00
u8 kvm_mmu_get_max_tdp_level ( void ) ;
2021-02-25 23:47:35 +03:00
void kvm_mmu_set_mmio_spte_mask ( u64 mmio_value , u64 mmio_mask , u64 access_mask ) ;
KVM: x86/mmu: Add shadow_me_value and repurpose shadow_me_mask
Intel Multi-Key Total Memory Encryption (MKTME) repurposes couple of
high bits of physical address bits as 'KeyID' bits. Intel Trust Domain
Extentions (TDX) further steals part of MKTME KeyID bits as TDX private
KeyID bits. TDX private KeyID bits cannot be set in any mapping in the
host kernel since they can only be accessed by software running inside a
new CPU isolated mode. And unlike to AMD's SME, host kernel doesn't set
any legacy MKTME KeyID bits to any mapping either. Therefore, it's not
legitimate for KVM to set any KeyID bits in SPTE which maps guest
memory.
KVM maintains shadow_zero_check bits to represent which bits must be
zero for SPTE which maps guest memory. MKTME KeyID bits should be set
to shadow_zero_check. Currently, shadow_me_mask is used by AMD to set
the sme_me_mask to SPTE, and shadow_me_shadow is excluded from
shadow_zero_check. So initializing shadow_me_mask to represent all
MKTME keyID bits doesn't work for VMX (as oppositely, they must be set
to shadow_zero_check).
Introduce a new 'shadow_me_value' to replace existing shadow_me_mask,
and repurpose shadow_me_mask as 'all possible memory encryption bits'.
The new schematic of them will be:
- shadow_me_value: the memory encryption bit(s) that will be set to the
SPTE (the original shadow_me_mask).
- shadow_me_mask: all possible memory encryption bits (which is a super
set of shadow_me_value).
- For now, shadow_me_value is supposed to be set by SVM and VMX
respectively, and it is a constant during KVM's life time. This
perhaps doesn't fit MKTME but for now host kernel doesn't support it
(and perhaps will never do).
- Bits in shadow_me_mask are set to shadow_zero_check, except the bits
in shadow_me_value.
Introduce a new helper kvm_mmu_set_me_spte_mask() to initialize them.
Replace shadow_me_mask with shadow_me_value in almost all code paths,
except the one in PT64_PERM_MASK, which is used by need_remote_flush()
to determine whether remote TLB flush is needed. This should still use
shadow_me_mask as any encryption bit change should need a TLB flush.
And for AMD, move initializing shadow_me_value/shadow_me_mask from
kvm_mmu_reset_all_pte_masks() to svm_hardware_setup().
Signed-off-by: Kai Huang <kai.huang@intel.com>
Message-Id: <f90964b93a3398b1cf1c56f510f3281e0709e2ab.1650363789.git.kai.huang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-19 14:17:03 +03:00
void kvm_mmu_set_me_spte_mask ( u64 me_value , u64 me_mask ) ;
2021-02-25 23:47:42 +03:00
void kvm_mmu_set_ept_masks ( bool has_ad_bits , bool has_exec_only ) ;
2013-06-07 12:51:25 +04:00
2021-06-10 02:42:33 +03:00
void kvm_init_mmu ( struct kvm_vcpu * vcpu ) ;
2021-06-22 20:56:59 +03:00
void kvm_init_shadow_npt_mmu ( struct kvm_vcpu * vcpu , unsigned long cr0 ,
unsigned long cr4 , u64 efer , gpa_t nested_cr3 ) ;
2017-03-30 12:55:30 +03:00
void kvm_init_shadow_ept_mmu ( struct kvm_vcpu * vcpu , bool execonly ,
2021-11-24 15:20:49 +03:00
int huge_page_level , bool accessed_dirty ,
gpa_t new_eptp ) ;
2017-06-09 06:13:40 +03:00
bool kvm_can_do_async_pf ( struct kvm_vcpu * vcpu ) ;
2017-07-14 04:30:40 +03:00
int kvm_handle_page_fault ( struct kvm_vcpu * vcpu , u64 error_code ,
2017-08-11 19:36:43 +03:00
u64 fault_address , char * insn , int insn_len ) ;
2023-04-05 03:26:08 +03:00
void __kvm_mmu_refresh_passthrough_bits ( struct kvm_vcpu * vcpu ,
struct kvm_mmu * mmu ) ;
2009-06-11 19:07:42 +04:00
2021-03-05 04:10:59 +03:00
int kvm_mmu_load ( struct kvm_vcpu * vcpu ) ;
void kvm_mmu_unload ( struct kvm_vcpu * vcpu ) ;
2022-02-25 21:22:45 +03:00
void kvm_mmu_free_obsolete_roots ( struct kvm_vcpu * vcpu ) ;
2021-03-05 04:10:59 +03:00
void kvm_mmu_sync_roots ( struct kvm_vcpu * vcpu ) ;
2021-10-19 14:01:54 +03:00
void kvm_mmu_sync_prev_roots ( struct kvm_vcpu * vcpu ) ;
2023-07-29 04:35:20 +03:00
void kvm_mmu_track_write ( struct kvm_vcpu * vcpu , gpa_t gpa , const u8 * new ,
int bytes ) ;
2021-03-05 04:10:59 +03:00
2007-12-14 04:35:10 +03:00
static inline int kvm_mmu_reload ( struct kvm_vcpu * vcpu )
{
2022-02-21 17:28:33 +03:00
if ( likely ( vcpu - > arch . mmu - > root . hpa ! = INVALID_PAGE ) )
2007-12-14 04:35:10 +03:00
return 0 ;
return kvm_mmu_load ( vcpu ) ;
}
2018-06-28 00:59:13 +03:00
static inline unsigned long kvm_get_pcid ( struct kvm_vcpu * vcpu , gpa_t cr3 )
{
BUILD_BUG_ON ( ( X86_CR3_PCID_MASK & PAGE_MASK ) ! = 0 ) ;
2023-03-22 07:58:21 +03:00
return kvm_is_cr4_bit_set ( vcpu , X86_CR4_PCIDE )
2018-06-28 00:59:13 +03:00
? cr3 & X86_CR3_PCID_MASK
: 0 ;
}
static inline unsigned long kvm_get_active_pcid ( struct kvm_vcpu * vcpu )
{
return kvm_get_pcid ( vcpu , kvm_read_cr3 ( vcpu ) ) ;
}
KVM: x86: Virtualize LAM for user pointer
Add support to allow guests to set the new CR3 control bits for Linear
Address Masking (LAM) and add implementation to get untagged address for
user pointers.
LAM modifies the canonical check for 64-bit linear addresses, allowing
software to use the masked/ignored address bits for metadata. Hardware
masks off the metadata bits before using the linear addresses to access
memory. LAM uses two new CR3 non-address bits, LAM_U48 (bit 62) and
LAM_U57 (bit 61), to configure LAM for user pointers. LAM also changes
VMENTER to allow both bits to be set in VMCS's HOST_CR3 and GUEST_CR3 for
virtualization.
When EPT is on, CR3 is not trapped by KVM and it's up to the guest to set
any of the two LAM control bits. However, when EPT is off, the actual CR3
used by the guest is generated from the shadow MMU root which is different
from the CR3 that is *set* by the guest, and KVM needs to manually apply
any active control bits to VMCS's GUEST_CR3 based on the cached CR3 *seen*
by the guest.
KVM manually checks guest's CR3 to make sure it points to a valid guest
physical address (i.e. to support smaller MAXPHYSADDR in the guest). Extend
this check to allow the two LAM control bits to be set. After check, LAM
bits of guest CR3 will be stripped off to extract guest physical address.
In case of nested, for a guest which supports LAM, both VMCS12's HOST_CR3
and GUEST_CR3 are allowed to have the new LAM control bits set, i.e. when
L0 enters L1 to emulate a VMEXIT from L2 to L1 or when L0 enters L2
directly. KVM also manually checks VMCS12's HOST_CR3 and GUEST_CR3 being
valid physical address. Extend such check to allow the new LAM control bits
too.
Note, LAM doesn't have a global control bit to turn on/off LAM completely,
but purely depends on hardware's CPUID to determine it can be enabled or
not. That means, when EPT is on, even when KVM doesn't expose LAM to guest,
the guest can still set LAM control bits in CR3 w/o causing problem. This
is an unfortunate virtualization hole. KVM could choose to intercept CR3 in
this case and inject fault but this would hurt performance when running a
normal VM w/o LAM support. This is undesirable. Just choose to let the
guest do such illegal thing as the worst case is guest being killed when
KVM eventually find out such illegal behaviour and that the guest is
misbehaving.
Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com>
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
Reviewed-by: Kai Huang <kai.huang@intel.com>
Reviewed-by: Chao Gao <chao.gao@intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Link: https://lore.kernel.org/r/20230913124227.12574-12-binbin.wu@linux.intel.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-09-13 15:42:22 +03:00
static inline unsigned long kvm_get_active_cr3_lam_bits ( struct kvm_vcpu * vcpu )
{
2023-09-13 15:42:24 +03:00
if ( ! guest_can_use ( vcpu , X86_FEATURE_LAM ) )
KVM: x86: Virtualize LAM for user pointer
Add support to allow guests to set the new CR3 control bits for Linear
Address Masking (LAM) and add implementation to get untagged address for
user pointers.
LAM modifies the canonical check for 64-bit linear addresses, allowing
software to use the masked/ignored address bits for metadata. Hardware
masks off the metadata bits before using the linear addresses to access
memory. LAM uses two new CR3 non-address bits, LAM_U48 (bit 62) and
LAM_U57 (bit 61), to configure LAM for user pointers. LAM also changes
VMENTER to allow both bits to be set in VMCS's HOST_CR3 and GUEST_CR3 for
virtualization.
When EPT is on, CR3 is not trapped by KVM and it's up to the guest to set
any of the two LAM control bits. However, when EPT is off, the actual CR3
used by the guest is generated from the shadow MMU root which is different
from the CR3 that is *set* by the guest, and KVM needs to manually apply
any active control bits to VMCS's GUEST_CR3 based on the cached CR3 *seen*
by the guest.
KVM manually checks guest's CR3 to make sure it points to a valid guest
physical address (i.e. to support smaller MAXPHYSADDR in the guest). Extend
this check to allow the two LAM control bits to be set. After check, LAM
bits of guest CR3 will be stripped off to extract guest physical address.
In case of nested, for a guest which supports LAM, both VMCS12's HOST_CR3
and GUEST_CR3 are allowed to have the new LAM control bits set, i.e. when
L0 enters L1 to emulate a VMEXIT from L2 to L1 or when L0 enters L2
directly. KVM also manually checks VMCS12's HOST_CR3 and GUEST_CR3 being
valid physical address. Extend such check to allow the new LAM control bits
too.
Note, LAM doesn't have a global control bit to turn on/off LAM completely,
but purely depends on hardware's CPUID to determine it can be enabled or
not. That means, when EPT is on, even when KVM doesn't expose LAM to guest,
the guest can still set LAM control bits in CR3 w/o causing problem. This
is an unfortunate virtualization hole. KVM could choose to intercept CR3 in
this case and inject fault but this would hurt performance when running a
normal VM w/o LAM support. This is undesirable. Just choose to let the
guest do such illegal thing as the worst case is guest being killed when
KVM eventually find out such illegal behaviour and that the guest is
misbehaving.
Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Co-developed-by: Binbin Wu <binbin.wu@linux.intel.com>
Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com>
Reviewed-by: Kai Huang <kai.huang@intel.com>
Reviewed-by: Chao Gao <chao.gao@intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Link: https://lore.kernel.org/r/20230913124227.12574-12-binbin.wu@linux.intel.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
2023-09-13 15:42:22 +03:00
return 0 ;
return kvm_read_cr3 ( vcpu ) & ( X86_CR3_LAM_U48 | X86_CR3_LAM_U57 ) ;
}
2020-03-03 12:11:10 +03:00
static inline void kvm_mmu_load_pgd ( struct kvm_vcpu * vcpu )
2018-06-28 00:59:08 +03:00
{
2022-02-21 17:28:33 +03:00
u64 root_hpa = vcpu - > arch . mmu - > root . hpa ;
2020-07-16 06:41:18 +03:00
if ( ! VALID_PAGE ( root_hpa ) )
return ;
2024-05-07 16:31:02 +03:00
kvm_x86_call ( load_mmu_pgd ) ( vcpu , root_hpa ,
vcpu - > arch . mmu - > root_role . level ) ;
2020-02-07 01:14:34 +03:00
}
2023-04-05 03:26:08 +03:00
static inline void kvm_mmu_refresh_passthrough_bits ( struct kvm_vcpu * vcpu ,
struct kvm_mmu * mmu )
{
/*
* When EPT is enabled , KVM may passthrough CR0 . WP to the guest , i . e .
* @ mmu ' s snapshot of CR0 . WP and thus all related paging metadata may
* be stale . Refresh CR0 . WP and the metadata on - demand when checking
* for permission faults . Exempt nested MMUs , i . e . MMUs for shadowing
* nEPT and nNPT , as CR0 . WP is ignored in both cases . Note , KVM does
* need to refresh nested_mmu , a . k . a . the walker used to translate L2
* GVAs to GPAs , as that " MMU " needs to honor L2 ' s CR0 . WP .
*/
if ( ! tdp_enabled | | mmu = = & vcpu - > arch . guest_mmu )
return ;
__kvm_mmu_refresh_passthrough_bits ( vcpu , mmu ) ;
}
KVM: MMU: Optimize pte permission checks
walk_addr_generic() permission checks are a maze of branchy code, which is
performed four times per lookup. It depends on the type of access, efer.nxe,
cr0.wp, cr4.smep, and in the near future, cr4.smap.
Optimize this away by precalculating all variants and storing them in a
bitmap. The bitmap is recalculated when rarely-changing variables change
(cr0, cr4) and is indexed by the often-changing variables (page fault error
code, pte access permissions).
The permission check is moved to the end of the loop, otherwise an SMEP
fault could be reported as a false positive, when PDE.U=1 but PTE.U=0.
Noted by Xiao Guangrong.
The result is short, branch-free code.
Reviewed-by: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2012-09-12 15:52:00 +04:00
/*
2016-03-08 12:08:16 +03:00
* Check if a given access ( described through the I / D , W / R and U / S bits of a
* page fault error code pfec ) causes a permission fault with the given PTE
* access rights ( in ACC_ * format ) .
*
* Return zero if the access does not fault ; return the page fault error code
* if the access faults .
KVM: MMU: Optimize pte permission checks
walk_addr_generic() permission checks are a maze of branchy code, which is
performed four times per lookup. It depends on the type of access, efer.nxe,
cr0.wp, cr4.smep, and in the near future, cr4.smap.
Optimize this away by precalculating all variants and storing them in a
bitmap. The bitmap is recalculated when rarely-changing variables change
(cr0, cr4) and is indexed by the often-changing variables (page fault error
code, pte access permissions).
The permission check is moved to the end of the loop, otherwise an SMEP
fault could be reported as a false positive, when PDE.U=1 but PTE.U=0.
Noted by Xiao Guangrong.
The result is short, branch-free code.
Reviewed-by: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2012-09-12 15:52:00 +04:00
*/
2016-03-08 12:08:16 +03:00
static inline u8 permission_fault ( struct kvm_vcpu * vcpu , struct kvm_mmu * mmu ,
2016-03-22 11:51:20 +03:00
unsigned pte_access , unsigned pte_pkey ,
2022-03-11 10:03:41 +03:00
u64 access )
2011-07-11 23:23:20 +04:00
{
2022-03-11 10:03:41 +03:00
/* strip nested paging fault error codes */
unsigned int pfec = access ;
2024-05-07 16:31:02 +03:00
unsigned long rflags = kvm_x86_call ( get_rflags ) ( vcpu ) ;
2014-04-01 13:46:34 +04:00
/*
2022-03-11 10:03:44 +03:00
* For explicit supervisor accesses , SMAP is disabled if EFLAGS . AC = 1.
* For implicit supervisor accesses , SMAP cannot be overridden .
2014-04-01 13:46:34 +04:00
*
2022-03-11 10:03:44 +03:00
* SMAP works on supervisor accesses only , and not_smap can
* be set or not set when user access with neither has any bearing
* on the result .
2014-04-01 13:46:34 +04:00
*
2022-03-11 10:03:44 +03:00
* We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit ;
* this bit will always be zero in pfec , but it will be one in index
* if SMAP checks are being disabled .
2014-04-01 13:46:34 +04:00
*/
2022-03-11 10:03:44 +03:00
u64 implicit_access = access & PFERR_IMPLICIT_ACCESS ;
bool not_smap = ( ( rflags & X86_EFLAGS_AC ) | implicit_access ) = = X86_EFLAGS_AC ;
2024-02-28 05:41:33 +03:00
int index = ( pfec | ( not_smap ? PFERR_RSVD_MASK : 0 ) ) > > 1 ;
2016-03-25 16:19:35 +03:00
u32 errcode = PFERR_PRESENT_MASK ;
2023-04-05 03:26:08 +03:00
bool fault ;
kvm_mmu_refresh_passthrough_bits ( vcpu , mmu ) ;
fault = ( mmu - > permissions [ index ] > > pte_access ) & 1 ;
2014-04-01 13:46:34 +04:00
2016-03-22 11:51:20 +03:00
WARN_ON ( pfec & ( PFERR_PK_MASK | PFERR_RSVD_MASK ) ) ;
if ( unlikely ( mmu - > pkru_mask ) ) {
u32 pkru_bits , offset ;
/*
* PKRU defines 32 bits , there are 16 domains and 2
* attribute bits per domain in pkru . pte_pkey is the
* index of the protection domain , so pte_pkey * 2 is
* is the index of the first bit for the domain .
*/
2017-08-24 00:14:38 +03:00
pkru_bits = ( vcpu - > arch . pkru > > ( pte_pkey * 2 ) ) & 3 ;
2016-03-22 11:51:20 +03:00
/* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
2024-02-28 05:41:33 +03:00
offset = ( pfec & ~ 1 ) | ( ( pte_access & PT_USER_MASK ) ? PFERR_RSVD_MASK : 0 ) ;
2016-03-22 11:51:20 +03:00
pkru_bits & = mmu - > pkru_mask > > offset ;
2016-03-25 16:19:35 +03:00
errcode | = - pkru_bits & PFERR_PK_MASK ;
2016-03-22 11:51:20 +03:00
fault | = ( pkru_bits ! = 0 ) ;
}
2016-03-25 16:19:35 +03:00
return - ( u32 ) fault & errcode ;
2011-07-11 23:23:20 +04:00
}
KVM: MMU: Optimize pte permission checks
walk_addr_generic() permission checks are a maze of branchy code, which is
performed four times per lookup. It depends on the type of access, efer.nxe,
cr0.wp, cr4.smep, and in the near future, cr4.smap.
Optimize this away by precalculating all variants and storing them in a
bitmap. The bitmap is recalculated when rarely-changing variables change
(cr0, cr4) and is indexed by the often-changing variables (page fault error
code, pte access permissions).
The permission check is moved to the end of the loop, otherwise an SMEP
fault could be reported as a false positive, when PDE.U=1 but PTE.U=0.
Noted by Xiao Guangrong.
The result is short, branch-free code.
Reviewed-by: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2012-09-12 15:52:00 +04:00
KVM: x86: Remove VMX support for virtualizing guest MTRR memtypes
Remove KVM's support for virtualizing guest MTRR memtypes, as full MTRR
adds no value, negatively impacts guest performance, and is a maintenance
burden due to it's complexity and oddities.
KVM's approach to virtualizating MTRRs make no sense, at all. KVM *only*
honors guest MTRR memtypes if EPT is enabled *and* the guest has a device
that may perform non-coherent DMA access. From a hardware virtualization
perspective of guest MTRRs, there is _nothing_ special about EPT. Legacy
shadowing paging doesn't magically account for guest MTRRs, nor does NPT.
Unwinding and deciphering KVM's murky history, the MTRR virtualization
code appears to be the result of misdiagnosed issues when EPT + VT-d with
passthrough devices was enabled years and years ago. And importantly, the
underlying bugs that were fudged around by honoring guest MTRR memtypes
have since been fixed (though rather poorly in some cases).
The zapping GFNs logic in the MTRR virtualization code came from:
commit efdfe536d8c643391e19d5726b072f82964bfbdb
Author: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Date: Wed May 13 14:42:27 2015 +0800
KVM: MMU: fix MTRR update
Currently, whenever guest MTRR registers are changed
kvm_mmu_reset_context is called to switch to the new root shadow page
table, however, it's useless since:
1) the cache type is not cached into shadow page's attribute so that
the original root shadow page will be reused
2) the cache type is set on the last spte, that means we should sync
the last sptes when MTRR is changed
This patch fixs this issue by drop all the spte in the gfn range which
is being updated by MTRR
which was a fix for:
commit 0bed3b568b68e5835ef5da888a372b9beabf7544
Author: Sheng Yang <sheng@linux.intel.com>
AuthorDate: Thu Oct 9 16:01:54 2008 +0800
Commit: Avi Kivity <avi@redhat.com>
CommitDate: Wed Dec 31 16:51:44 2008 +0200
KVM: Improve MTRR structure
As well as reset mmu context when set MTRR.
which was part of a "MTRR/PAT support for EPT" series that also added:
+ if (mt_mask) {
+ mt_mask = get_memory_type(vcpu, gfn) <<
+ kvm_x86_ops->get_mt_mask_shift();
+ spte |= mt_mask;
+ }
where get_memory_type() was a truly gnarly helper to retrieve the guest
MTRR memtype for a given memtype. And *very* subtly, at the time of that
change, KVM *always* set VMX_EPT_IGMT_BIT,
kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
VMX_EPT_WRITABLE_MASK |
VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT |
VMX_EPT_IGMT_BIT);
which came in via:
commit 928d4bf747e9c290b690ff515d8f81e8ee226d97
Author: Sheng Yang <sheng@linux.intel.com>
AuthorDate: Thu Nov 6 14:55:45 2008 +0800
Commit: Avi Kivity <avi@redhat.com>
CommitDate: Tue Nov 11 21:00:37 2008 +0200
KVM: VMX: Set IGMT bit in EPT entry
There is a potential issue that, when guest using pagetable without vmexit when
EPT enabled, guest would use PAT/PCD/PWT bits to index PAT msr for it's memory,
which would be inconsistent with host side and would cause host MCE due to
inconsistent cache attribute.
The patch set IGMT bit in EPT entry to ignore guest PAT and use WB as default
memory type to protect host (notice that all memory mapped by KVM should be WB).
Note the CommitDates! The AuthorDates strongly suggests Sheng Yang added
the whole "ignoreIGMT things as a bug fix for issues that were detected
during EPT + VT-d + passthrough enabling, but it was applied earlier
because it was a generic fix.
Jumping back to 0bed3b568b68 ("KVM: Improve MTRR structure"), the other
relevant code, or rather lack thereof, is the handling of *host* MMIO.
That fix came in a bit later, but given the author and timing, it's safe
to say it was all part of the same EPT+VT-d enabling mess.
commit 2aaf69dcee864f4fb6402638dd2f263324ac839f
Author: Sheng Yang <sheng@linux.intel.com>
AuthorDate: Wed Jan 21 16:52:16 2009 +0800
Commit: Avi Kivity <avi@redhat.com>
CommitDate: Sun Feb 15 02:47:37 2009 +0200
KVM: MMU: Map device MMIO as UC in EPT
Software are not allow to access device MMIO using cacheable memory type, the
patch limit MMIO region with UC and WC(guest can select WC using PAT and
PCD/PWT).
In addition to the host MMIO and IGMT issues, KVM's MTRR virtualization
was obviously never tested on NPT until much later, which lends further
credence to the theory/argument that this was all the result of
misdiagnosed issues.
Discussion from the EPT+MTRR enabling thread[*] more or less confirms that
Sheng Yang was trying to resolve issues with passthrough MMIO.
* Sheng Yang
: Do you mean host(qemu) would access this memory and if we set it to guest
: MTRR, host access would be broken? We would cover this in our shadow MTRR
: patch, for we encountered this in video ram when doing some experiment with
: VGA assignment.
And in the same thread, there's also what appears to be confirmation of
Intel running into issues with Windows XP related to a guest device driver
mapping DMA with WC in the PAT.
* Avi Kavity
: Sheng Yang wrote:
: > Yes... But it's easy to do with assigned devices' mmio, but what if guest
: > specific some non-mmio memory's memory type? E.g. we have met one issue in
: > Xen, that a assigned-device's XP driver specific one memory region as buffer,
: > and modify the memory type then do DMA.
: >
: > Only map MMIO space can be first step, but I guess we can modify assigned
: > memory region memory type follow guest's?
: >
:
: With ept/npt, we can't, since the memory type is in the guest's
: pagetable entries, and these are not accessible.
[*] https://lore.kernel.org/all/1223539317-32379-1-git-send-email-sheng@linux.intel.com
So, for the most part, what likely happened is that 15 years ago, a few
engineers (a) fixed a #MC problem by ignoring guest PAT and (b) initially
"fixed" passthrough device MMIO by emulating *guest* MTRRs. Except for
the below case, everything since then has been a result of those two
intertwined changes.
The one exception, which is actually yet more confirmation of all of the
above, is the revert of Paolo's attempt at "full" virtualization of guest
MTRRs:
commit 606decd67049217684e3cb5a54104d51ddd4ef35
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: Thu Oct 1 13:12:47 2015 +0200
Revert "KVM: x86: apply guest MTRR virtualization on host reserved pages"
This reverts commit fd717f11015f673487ffc826e59b2bad69d20fe5.
It was reported to cause Machine Check Exceptions (bug 104091).
...
commit fd717f11015f673487ffc826e59b2bad69d20fe5
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: Tue Jul 7 14:38:13 2015 +0200
KVM: x86: apply guest MTRR virtualization on host reserved pages
Currently guest MTRR is avoided if kvm_is_reserved_pfn returns true.
However, the guest could prefer a different page type than UC for
such pages. A good example is that pass-throughed VGA frame buffer is
not always UC as host expected.
This patch enables full use of virtual guest MTRRs.
I.e. Paolo tried to add back KVM's behavior before "Map device MMIO as UC
in EPT" and got the same result: machine checks, likely due to the guest
MTRRs not being trustworthy/sane at all times.
Note, Paolo also tried to enable MTRR virtualization on SVM+NPT, but that
too got reverted. Unfortunately, it doesn't appear that anyone ever found
a smoking gun, i.e. exactly why emulating guest MTRRs via NPT PAT caused
extremely slow boot times doesn't appear to have a definitive root cause.
commit fc07e76ac7ffa3afd621a1c3858a503386a14281
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: Thu Oct 1 13:20:22 2015 +0200
Revert "KVM: SVM: use NPT page attributes"
This reverts commit 3c2e7f7de3240216042b61073803b61b9b3cfb22.
Initializing the mapping from MTRR to PAT values was reported to
fail nondeterministically, and it also caused extremely slow boot
(due to caching getting disabled---bug 103321) with assigned devices.
...
commit 3c2e7f7de3240216042b61073803b61b9b3cfb22
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: Tue Jul 7 14:32:17 2015 +0200
KVM: SVM: use NPT page attributes
Right now, NPT page attributes are not used, and the final page
attribute depends solely on gPAT (which however is not synced
correctly), the guest MTRRs and the guest page attributes.
However, we can do better by mimicking what is done for VMX.
In the absence of PCI passthrough, the guest PAT can be ignored
and the page attributes can be just WB. If passthrough is being
used, instead, keep respecting the guest PAT, and emulate the guest
MTRRs through the PAT field of the nested page tables.
The only snag is that WP memory cannot be emulated correctly,
because Linux's default PAT setting only includes the other types.
In short, honoring guest MTRRs for VMX was initially a workaround of
sorts for KVM ignoring guest PAT *and* for KVM not forcing UC for host
MMIO. And while there *are* known cases where honoring guest MTRRs is
desirable, e.g. passthrough VGA frame buffers, the desired behavior in
that case is to get WC instead of UC, i.e. at this point it's for
performance, not correctness.
Furthermore, the complete absence of MTRR virtualization on NPT and
shadow paging proves that, while KVM theoretically can do better, it's
by no means necessary for correctnesss.
Lastly, since kernels mostly rely on firmware to do MTRR setup, and the
host typically provides guest firmware, honoring guest MTRRs is effectively
honoring *host* userspace memtypes, which is also backwards. I.e. it
would be far better for host userspace to communicate its desired memtype
directly to KVM (or perhaps indirectly via VMAs in the host kernel), not
through guest MTRRs.
Tested-by: Xiangfei Ma <xiangfeix.ma@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Link: https://lore.kernel.org/r/20240309010929.1403984-2-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
2024-03-09 04:09:25 +03:00
bool kvm_mmu_may_ignore_guest_pat ( void ) ;
2023-07-14 09:50:06 +03:00
2020-06-22 23:20:31 +03:00
int kvm_arch_write_log_dirty ( struct kvm_vcpu * vcpu ) ;
2019-11-04 22:26:00 +03:00
int kvm_mmu_post_init_vm ( struct kvm * kvm ) ;
void kvm_mmu_pre_destroy_vm ( struct kvm * kvm ) ;
2021-10-15 19:30:21 +03:00
static inline bool kvm_shadow_root_allocated ( struct kvm * kvm )
2021-05-18 20:34:13 +03:00
{
2021-05-18 20:34:14 +03:00
/*
2021-10-15 19:30:21 +03:00
* Read shadow_root_allocated before related pointers . Hence , threads
* reading shadow_root_allocated in any lock context are guaranteed to
* see the pointers . Pairs with smp_store_release in
* mmu_first_shadow_root_alloc .
2021-05-18 20:34:14 +03:00
*/
2021-10-15 19:30:21 +03:00
return smp_load_acquire ( & kvm - > arch . shadow_root_allocated ) ;
}
# ifdef CONFIG_X86_64
2022-09-21 20:35:37 +03:00
extern bool tdp_mmu_enabled ;
2021-10-15 19:30:21 +03:00
# else
2022-09-21 20:35:37 +03:00
# define tdp_mmu_enabled false
2021-10-15 19:30:21 +03:00
# endif
static inline bool kvm_memslots_have_rmaps ( struct kvm * kvm )
{
2022-09-21 20:35:37 +03:00
return ! tdp_mmu_enabled | | kvm_shadow_root_allocated ( kvm ) ;
2021-05-18 20:34:13 +03:00
}
2021-07-31 01:04:51 +03:00
static inline gfn_t gfn_to_index ( gfn_t gfn , gfn_t base_gfn , int level )
{
/* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
return ( gfn > > KVM_HPAGE_GFN_SHIFT ( level ) ) -
( base_gfn > > KVM_HPAGE_GFN_SHIFT ( level ) ) ;
}
static inline unsigned long
__kvm_mmu_slot_lpages ( struct kvm_memory_slot * slot , unsigned long npages ,
int level )
{
return gfn_to_index ( slot - > base_gfn + npages - 1 ,
slot - > base_gfn , level ) + 1 ;
}
static inline unsigned long
kvm_mmu_slot_lpages ( struct kvm_memory_slot * slot , int level )
{
return __kvm_mmu_slot_lpages ( slot , slot - > npages , level ) ;
}
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static inline void kvm_update_page_stats ( struct kvm * kvm , int level , int count )
{
atomic64_add ( count , & kvm - > stat . pages [ level - 1 ] ) ;
}
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gpa_t translate_nested_gpa ( struct kvm_vcpu * vcpu , gpa_t gpa , u64 access ,
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struct x86_exception * exception ) ;
static inline gpa_t kvm_translate_gpa ( struct kvm_vcpu * vcpu ,
struct kvm_mmu * mmu ,
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gpa_t gpa , u64 access ,
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struct x86_exception * exception )
{
if ( mmu ! = & vcpu - > arch . nested_mmu )
return gpa ;
return translate_nested_gpa ( vcpu , gpa , access , exception ) ;
}
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# endif
