2019-05-19 15:07:45 +03:00
# SPDX-License-Identifier: GPL-2.0-only
2017-10-16 21:04:33 +03:00
menu "IRQ chip support"
irqchip: add basic infrastructure
With the recent creation of the drivers/irqchip/ directory, it is
desirable to move irq controller drivers here. At the moment, the only
driver here is irq-bcm2835, the driver for the irq controller found in
the ARM BCM2835 SoC, present in Rasberry Pi systems. This irq
controller driver was exporting its initialization function and its
irq handling function through a header file in
<linux/irqchip/bcm2835.h>.
When proposing to also move another irq controller driver in
drivers/irqchip, Rob Herring raised the very valid point that moving
things to drivers/irqchip was good in order to remove more stuff from
arch/arm, but if it means adding gazillions of headers files in
include/linux/irqchip/, it would not be very nice.
So, upon the suggestion of Rob Herring and Arnd Bergmann, this commit
introduces a small infrastructure that defines a central
irqchip_init() function in drivers/irqchip/irqchip.c, which is meant
to be called as the ->init_irq() callback of ARM platforms. This
function calls of_irq_init() with an array of match strings and init
functions generated from a special linker section.
Note that the irq controller driver initialization function is
responsible for setting the global handle_arch_irq() variable, so that
ARM platforms no longer have to define the ->handle_irq field in their
DT_MACHINE structure.
A global header, <linux/irqchip.h> is also added to expose the single
irqchip_init() function to the reset of the kernel.
A further commit moves the BCM2835 irq controller driver to this new
small infrastructure, therefore removing the include/linux/irqchip/
directory.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[rob.herring: reword commit message to reflect use of linker sections.]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-11-21 02:00:52 +04:00
config IRQCHIP
def_bool y
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depends on (OF_IRQ || ACPI_GENERIC_GSI)
irqchip: add basic infrastructure
With the recent creation of the drivers/irqchip/ directory, it is
desirable to move irq controller drivers here. At the moment, the only
driver here is irq-bcm2835, the driver for the irq controller found in
the ARM BCM2835 SoC, present in Rasberry Pi systems. This irq
controller driver was exporting its initialization function and its
irq handling function through a header file in
<linux/irqchip/bcm2835.h>.
When proposing to also move another irq controller driver in
drivers/irqchip, Rob Herring raised the very valid point that moving
things to drivers/irqchip was good in order to remove more stuff from
arch/arm, but if it means adding gazillions of headers files in
include/linux/irqchip/, it would not be very nice.
So, upon the suggestion of Rob Herring and Arnd Bergmann, this commit
introduces a small infrastructure that defines a central
irqchip_init() function in drivers/irqchip/irqchip.c, which is meant
to be called as the ->init_irq() callback of ARM platforms. This
function calls of_irq_init() with an array of match strings and init
functions generated from a special linker section.
Note that the irq controller driver initialization function is
responsible for setting the global handle_arch_irq() variable, so that
ARM platforms no longer have to define the ->handle_irq field in their
DT_MACHINE structure.
A global header, <linux/irqchip.h> is also added to expose the single
irqchip_init() function to the reset of the kernel.
A further commit moves the BCM2835 irq controller driver to this new
small infrastructure, therefore removing the include/linux/irqchip/
directory.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[rob.herring: reword commit message to reflect use of linker sections.]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-11-21 02:00:52 +04:00
2012-11-21 07:21:40 +04:00
config ARM_GIC
bool
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depends on OF
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
2012-11-21 07:21:40 +04:00
irqchip/gic: Add platform driver for non-root GICs that require RPM
Add a platform driver to support non-root GICs that require runtime
power-management. Currently, only non-root GICs are supported because
the functions, smp_cross_call() and set_handle_irq(), that need to
be called for a root controller are located in the __init section and
so cannot be called by the platform driver.
The GIC platform driver re-uses many functions from the existing GIC
driver including some functions to save and restore the GIC context
during power transitions. The functions for saving and restoring the
GIC context are currently only defined if CONFIG_CPU_PM is enabled and
to ensure that these functions are always defined when the platform
driver is enabled, a dependency on CONFIG_ARM_GIC_PM (which selects the
platform driver) has been added.
In order to re-use the private GIC initialisation code, a new public
function, gic_of_init_child(), has been added which calls various
private functions to initialise the GIC. This is different from the
existing gic_of_init() because it only supports non-root GICs (ie. does
not call smp_cross_call() is set_handle_irq()) and is not located in
the __init section (so can be used by platform drivers). Furthermore,
gic_of_init_child() dynamically allocates memory for the GIC chip data
which is also different from gic_of_init().
There is no specific suspend handling for GICs registered as platform
devices. Non-wakeup interrupts will be disabled by the kernel during
late suspend, however, this alone will not power down the GIC if
interrupts have been requested and not freed. Therefore, requestors of
non-wakeup interrupts will need to free them on entering suspend in
order to power-down the GIC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-06-07 18:12:34 +03:00
config ARM_GIC_PM
bool
depends on PM
select ARM_GIC
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config ARM_GIC_MAX_NR
int
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depends on ARM_GIC
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default 2 if ARCH_REALVIEW
default 1
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config ARM_GIC_V2M
bool
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depends on PCI
select ARM_GIC
select PCI_MSI
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config GIC_NON_BANKED
bool
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config ARM_GIC_V3
bool
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
irqchip/gicv3: Workaround for NVIDIA erratum T241-FABRIC-4
The T241 platform suffers from the T241-FABRIC-4 erratum which causes
unexpected behavior in the GIC when multiple transactions are received
simultaneously from different sources. This hardware issue impacts
NVIDIA server platforms that use more than two T241 chips
interconnected. Each chip has support for 320 {E}SPIs.
This issue occurs when multiple packets from different GICs are
incorrectly interleaved at the target chip. The erratum text below
specifies exactly what can cause multiple transfer packets susceptible
to interleaving and GIC state corruption. GIC state corruption can
lead to a range of problems, including kernel panics, and unexpected
behavior.
>From the erratum text:
"In some cases, inter-socket AXI4 Stream packets with multiple
transfers, may be interleaved by the fabric when presented to ARM
Generic Interrupt Controller. GIC expects all transfers of a packet
to be delivered without any interleaving.
The following GICv3 commands may result in multiple transfer packets
over inter-socket AXI4 Stream interface:
- Register reads from GICD_I* and GICD_N*
- Register writes to 64-bit GICD registers other than GICD_IROUTERn*
- ITS command MOVALL
Multiple commands in GICv4+ utilize multiple transfer packets,
including VMOVP, VMOVI, VMAPP, and 64-bit register accesses."
This issue impacts system configurations with more than 2 sockets,
that require multi-transfer packets to be sent over inter-socket
AXI4 Stream interface between GIC instances on different sockets.
GICv4 cannot be supported. GICv3 SW model can only be supported
with the workaround. Single and Dual socket configurations are not
impacted by this issue and support GICv3 and GICv4."
Link: https://developer.nvidia.com/docs/t241-fabric-4/nvidia-t241-fabric-4-errata.pdf
Writing to the chip alias region of the GICD_In{E} registers except
GICD_ICENABLERn has an equivalent effect as writing to the global
distributor. The SPI interrupt deactivate path is not impacted by
the erratum.
To fix this problem, implement a workaround that ensures read accesses
to the GICD_In{E} registers are directed to the chip that owns the
SPI, and disable GICv4.x features. To simplify code changes, the
gic_configure_irq() function uses the same alias region for both read
and write operations to GICD_ICFGR.
Co-developed-by: Vikram Sethi <vsethi@nvidia.com>
Signed-off-by: Vikram Sethi <vsethi@nvidia.com>
Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com> (for SMCCC/SOC ID bits)
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230319024314.3540573-2-sdonthineni@nvidia.com
2023-03-19 05:43:14 +03:00
select HAVE_ARM_SMCCC_DISCOVERY
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config ARM_GIC_V3_ITS
bool
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select GENERIC_MSI_IRQ
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default ARM_GIC_V3
config ARM_GIC_V3_ITS_PCI
bool
depends on ARM_GIC_V3_ITS
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depends on PCI
depends on PCI_MSI
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default ARM_GIC_V3_ITS
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config ARM_GIC_V3_ITS_FSL_MC
bool
depends on ARM_GIC_V3_ITS
depends on FSL_MC_BUS
default ARM_GIC_V3_ITS
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config ARM_NVIC
bool
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_CHIP
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config ARM_VIC
bool
select IRQ_DOMAIN
config ARM_VIC_NR
int
default 4 if ARCH_S5PV210
default 2
depends on ARM_VIC
help
The maximum number of VICs available in the system, for
power management.
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config ARMADA_370_XP_IRQ
bool
select GENERIC_IRQ_CHIP
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select PCI_MSI if PCI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config ALPINE_MSI
bool
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depends on PCI
select PCI_MSI
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select GENERIC_IRQ_CHIP
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config AL_FIC
bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
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depends on OF
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select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
help
Support Amazon's Annapurna Labs Fabric Interrupt Controller.
2014-07-10 21:14:18 +04:00
config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select SPARSE_IRQ
config ATMEL_AIC5_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select SPARSE_IRQ
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config I8259
bool
select IRQ_DOMAIN
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config BCM6345_L1_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-25 20:49:06 +03:00
config BCM7038_L1_IRQ
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tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
depends on ARCH_BRCMSTB || BMIPS_GENERIC
default ARCH_BRCMSTB || BMIPS_GENERIC
IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-25 20:49:06 +03:00
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-25 20:49:06 +03:00
2014-11-07 09:44:27 +03:00
config BCM7120_L2_IRQ
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tristate "Broadcom STB 7120-style L2 interrupt controller driver"
depends on ARCH_BRCMSTB || BMIPS_GENERIC
default ARCH_BRCMSTB || BMIPS_GENERIC
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select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config BRCMSTB_L2_IRQ
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tristate "Broadcom STB generic L2 interrupt controller driver"
depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
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select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config DAVINCI_CP_INTC
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config DW_APB_ICTL
bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN_HIERARCHY
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2017-03-18 19:53:24 +03:00
config FARADAY_FTINTC010
bool
select IRQ_DOMAIN
select SPARSE_IRQ
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config HISILICON_IRQ_MBIGEN
bool
select ARM_GIC_V3
select ARM_GIC_V3_ITS
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config IMGPDC_IRQ
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config IXP4XX_IRQ
bool
select IRQ_DOMAIN
select SPARSE_IRQ
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config MADERA_IRQ
tristate
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config IRQ_MIPS_CPU
bool
select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config CLPS711X_IRQCHIP
bool
depends on ARCH_CLPS711X
select IRQ_DOMAIN
select SPARSE_IRQ
default y
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config OMPIC
bool
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config OR1K_PIC
bool
select IRQ_DOMAIN
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config OMAP_IRQCHIP
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config ORION_IRQCHIP
bool
select IRQ_DOMAIN
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config PIC32_EVIC
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
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config JCORE_AIC
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bool "J-Core integrated AIC" if COMPILE_TEST
depends on OF
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select IRQ_DOMAIN
help
Support for the J-Core integrated AIC.
2018-12-10 20:35:43 +03:00
config RDA_INTC
bool
select IRQ_DOMAIN
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config RENESAS_INTC_IRQPIN
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bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
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select IRQ_DOMAIN
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help
Enable support for the Renesas Interrupt Controller for external
interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
2013-02-18 18:28:34 +04:00
2013-02-27 12:15:01 +04:00
config RENESAS_IRQC
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bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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help
Enable support for the Renesas Interrupt Controller for external
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devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
2013-02-27 12:15:01 +04:00
2019-05-27 15:17:11 +03:00
config RENESAS_RZA1_IRQC
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bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
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select IRQ_DOMAIN_HIERARCHY
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help
Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
to 8 external interrupts with configurable sense select.
2019-05-27 15:17:11 +03:00
2022-07-07 21:23:11 +03:00
config RENESAS_RZG2L_IRQC
bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN_HIERARCHY
help
Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
for external devices.
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config SL28CPLD_INTC
bool "Kontron sl28cpld IRQ controller"
depends on MFD_SL28CPLD=y || COMPILE_TEST
select REGMAP_IRQ
help
Interrupt controller driver for the board management controller
found on the Kontron sl28 CPLD.
2015-02-18 18:13:58 +03:00
config ST_IRQCHIP
bool
select REGMAP
select MFD_SYSCON
help
Enables SysCfg Controlled IRQs on STi based platforms.
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config SUN4I_INTC
bool
config SUN6I_R_INTC
bool
select IRQ_DOMAIN_HIERARCHY
select IRQ_FASTEOI_HIERARCHY_HANDLERS
config SUNXI_NMI_INTC
bool
select GENERIC_IRQ_CHIP
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config TB10X_IRQC
bool
select IRQ_DOMAIN
select GENERIC_IRQ_CHIP
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config TS4800_IRQ
tristate "TS-4800 IRQ controller"
select IRQ_DOMAIN
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depends on HAS_IOMEM
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depends on SOC_IMX51 || COMPILE_TEST
2015-12-21 23:11:23 +03:00
help
Support for the TS-4800 FPGA IRQ controller
2012-11-01 01:04:31 +04:00
config VERSATILE_FPGA_IRQ
bool
select IRQ_DOMAIN
config VERSATILE_FPGA_IRQ_NR
int
default 4
depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
bool
select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
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config XILINX_INTC
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bool "Xilinx Interrupt Controller IP"
2022-06-30 14:10:08 +03:00
depends on OF_ADDRESS
2016-11-14 15:13:45 +03:00
select IRQ_DOMAIN
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help
Support for the Xilinx Interrupt Controller IP core.
This is used as a primary controller with MicroBlaze and can also
be used as a secondary chained controller on other platforms.
2016-11-14 15:13:45 +03:00
2013-12-03 14:27:23 +04:00
config IRQ_CROSSBAR
bool
help
2014-09-18 07:09:42 +04:00
Support for a CROSSBAR ip that precedes the main interrupt controller.
2013-12-03 14:27:23 +04:00
The primary irqchip invokes the crossbar's callback which inturn allocates
a free irq and configures the IP. Thus the peripheral interrupts are
routed to one of the free irqchip interrupt lines.
2014-07-23 18:40:30 +04:00
config KEYSTONE_IRQ
tristate "Keystone 2 IRQ controller IP"
depends on ARCH_KEYSTONE
help
Support for Texas Instruments Keystone 2 IRQ controller IP which
is part of the Keystone 2 IPC mechanism
2014-09-19 01:47:19 +04:00
config MIPS_GIC
bool
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select GENERIC_IRQ_IPI if SMP
select IRQ_DOMAIN_HIERARCHY
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select MIPS_CM
2015-05-09 20:30:47 +03:00
2015-05-24 18:11:31 +03:00
config INGENIC_IRQ
bool
depends on MACH_INGENIC
default y
2015-06-27 22:44:34 +03:00
2019-07-24 20:16:08 +03:00
config INGENIC_TCU_IRQ
bool "Ingenic JZ47xx TCU interrupt controller"
default MACH_INGENIC
depends on MIPS || COMPILE_TEST
select MFD_SYSCON
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select GENERIC_IRQ_CHIP
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help
Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
JZ47xx SoCs.
If unsure, say N.
2015-08-24 22:04:15 +03:00
config IMX_GPCV2
bool
select IRQ_DOMAIN
help
Enables the wakeup IRQs for IMX platforms with GPCv2 block
2015-10-12 22:15:34 +03:00
config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
2016-02-19 16:34:43 +03:00
2018-03-22 18:15:24 +03:00
config MSCC_OCELOT_IRQ
bool
select IRQ_DOMAIN
select GENERIC_IRQ_CHIP
2017-06-21 16:29:14 +03:00
config MVEBU_GICP
bool
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config MVEBU_ICU
bool
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config MVEBU_ODMI
bool
2022-11-11 16:54:40 +03:00
select GENERIC_MSI_IRQ
irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 11:57:53 +03:00
2016-08-05 17:55:19 +03:00
config MVEBU_PIC
bool
2018-10-01 17:13:51 +03:00
config MVEBU_SEI
bool
irqchip: Add support for Layerscape external interrupt lines
The LS1021A allows inverting the polarity of six interrupt lines
IRQ[0:5] via the scfg_intpcr register, effectively allowing
IRQ_TYPE_LEVEL_LOW and IRQ_TYPE_EDGE_FALLING for those. We just need to
check the type, set the relevant bit in INTPCR accordingly, and fixup
the type argument before calling the GIC's irq_set_type.
In fact, the power-on-reset value of the INTPCR register on the LS1021A
is so that all six lines have their polarity inverted. Hence any
hardware connected to those lines is unusable without this: If the line
is indeed active low, the generic GIC code will reject an irq spec with
IRQ_TYPE_LEVEL_LOW, while if the line is active high, we must obviously
disable the polarity inversion (writing 0 to the relevant bit) before
unmasking the interrupt.
Some other Layerscape SOCs (LS1043A, LS1046A) have a similar feature,
just with a different number of external interrupt lines (and a
different POR value for the INTPCR register). This driver should be
prepared for supporting those by properly filling out the device tree
node. I have the reference manuals for all three boards, but I've only
tested the driver on an LS1021A.
Unfortunately, the Kconfig symbol ARCH_LAYERSCAPE only exists on
arm64, so do as is done for irq-ls-scfg-msi.c: introduce a new symbol
which is set when either ARCH_LAYERSCAPE or SOC_LS1021A is set.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20191107122115.6244-3-linux@rasmusvillemoes.dk
2019-11-07 15:21:15 +03:00
config LS_EXTIRQ
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
select MFD_SYSCON
2016-03-23 14:08:20 +03:00
config LS_SCFG_MSI
def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
2023-01-11 13:05:54 +03:00
depends on PCI_MSI
2016-03-23 14:08:20 +03:00
irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 11:57:53 +03:00
config PARTITION_PERCPU
bool
2016-05-19 19:46:18 +03:00
2016-09-20 19:00:57 +03:00
config STM32_EXTI
bool
select IRQ_DOMAIN
2017-11-06 20:03:31 +03:00
select GENERIC_IRQ_CHIP
2017-02-03 02:23:59 +03:00
config QCOM_IRQ_COMBINER
bool "QCOM IRQ combiner support"
depends on ARCH_QCOM && ACPI
select IRQ_DOMAIN_HIERARCHY
help
Say yes here to add support for the IRQ combiner devices embedded
in Qualcomm Technologies chips.
2017-08-23 04:31:47 +03:00
config IRQ_UNIPHIER_AIDET
bool "UniPhier AIDET support" if COMPILE_TEST
depends on ARCH_UNIPHIER || COMPILE_TEST
default ARCH_UNIPHIER
select IRQ_DOMAIN_HIERARCHY
help
Support for the UniPhier AIDET (ARM Interrupt Detector).
2017-10-16 21:04:33 +03:00
2017-09-18 16:46:10 +03:00
config MESON_IRQ_GPIO
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tristate "Meson GPIO Interrupt Multiplexer"
depends on ARCH_MESON || COMPILE_TEST
default ARCH_MESON
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select IRQ_DOMAIN_HIERARCHY
help
Support Meson SoC Family GPIO Interrupt Multiplexer
2017-12-29 18:41:46 +03:00
config GOLDFISH_PIC
bool "Goldfish programmable interrupt controller"
depends on MIPS && (GOLDFISH || COMPILE_TEST)
2021-09-05 19:25:19 +03:00
select GENERIC_IRQ_CHIP
2017-12-29 18:41:46 +03:00
select IRQ_DOMAIN
help
Say yes here to enable Goldfish interrupt controller driver used
for Goldfish based virtual platforms.
2018-02-28 20:27:29 +03:00
config QCOM_PDC
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tristate "QCOM PDC"
2018-02-28 20:27:29 +03:00
depends on ARCH_QCOM
select IRQ_DOMAIN_HIERARCHY
help
Power Domain Controller driver to manage and configure wakeup
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
2022-03-08 11:05:34 +03:00
config QCOM_MPM
tristate "QCOM MPM"
depends on ARCH_QCOM
2022-03-17 16:19:56 +03:00
depends on MAILBOX
2022-03-08 11:05:34 +03:00
select IRQ_DOMAIN_HIERARCHY
help
MSM Power Manager driver to manage and configure wakeup
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
2018-09-16 10:57:14 +03:00
config CSKY_MPINTC
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bool
2018-09-16 10:57:14 +03:00
depends on CSKY
help
Say yes here to enable C-SKY SMP interrupt controller driver used
for C-SKY SMP system.
2020-01-29 05:25:14 +03:00
In fact it's not mmio map in hardware and it uses ld/st to visit the
2018-09-16 10:57:14 +03:00
controller's register inside CPU.
2018-09-16 10:57:14 +03:00
config CSKY_APB_INTC
bool "C-SKY APB Interrupt Controller"
depends on CSKY
help
Say yes here to enable C-SKY APB interrupt controller driver used
2020-01-29 05:25:14 +03:00
by C-SKY single core SOC system. It uses mmio map apb-bus to visit
2018-09-16 10:57:14 +03:00
the controller's register.
2018-12-17 17:01:20 +03:00
config IMX_IRQSTEER
bool "i.MX IRQSTEER support"
depends on ARCH_MXC || COMPILE_TEST
default ARCH_MXC
select IRQ_DOMAIN
help
Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
2020-01-17 09:10:10 +03:00
config IMX_INTMUX
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bool "i.MX INTMUX support" if COMPILE_TEST
default y if ARCH_MXC
2020-01-17 09:10:10 +03:00
select IRQ_DOMAIN
help
Support for the i.MX INTMUX interrupt multiplexer.
2022-09-22 19:12:43 +03:00
config IMX_MU_MSI
tristate "i.MX MU used as MSI controller"
depends on OF && HAS_IOMEM
2022-10-04 19:22:30 +03:00
depends on ARCH_MXC || COMPILE_TEST
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default m if ARCH_MXC
select IRQ_DOMAIN
select IRQ_DOMAIN_HIERARCHY
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select GENERIC_MSI_IRQ
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help
2022-10-04 19:22:30 +03:00
Provide a driver for the i.MX Messaging Unit block used as a
CPU-to-CPU MSI controller. This requires a specially crafted DT
to make use of this driver.
2022-09-22 19:12:43 +03:00
If unsure, say N
2019-02-01 09:22:35 +03:00
config LS1X_IRQ
bool "Loongson-1 Interrupt Controller"
depends on MACH_LOONGSON32
default y
select IRQ_DOMAIN
select GENERIC_IRQ_CHIP
help
Support for the Loongson-1 platform Interrupt Controller.
2019-04-30 13:12:25 +03:00
config TI_SCI_INTR_IRQCHIP
bool
depends on TI_SCI_PROTOCOL
select IRQ_DOMAIN_HIERARCHY
help
This enables the irqchip driver support for K3 Interrupt router
over TI System Control Interface available on some new TI's SoCs.
If you wish to use interrupt router irq resources managed by the
TI System Controller, say Y here. Otherwise, say N.
2019-04-30 13:12:27 +03:00
config TI_SCI_INTA_IRQCHIP
bool
depends on TI_SCI_PROTOCOL
select IRQ_DOMAIN_HIERARCHY
2019-04-30 13:12:29 +03:00
select TI_SCI_INTA_MSI_DOMAIN
2019-04-30 13:12:27 +03:00
help
This enables the irqchip driver support for K3 Interrupt aggregator
over TI System Control Interface available on some new TI's SoCs.
If you wish to use interrupt aggregator irq resources managed by the
TI System Controller, say Y here. Otherwise, say N.
2020-09-16 19:36:03 +03:00
config TI_PRUSS_INTC
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tristate
depends on TI_PRUSS
default TI_PRUSS
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select IRQ_DOMAIN
help
This enables support for the PRU-ICSS Local Interrupt Controller
present within a PRU-ICSS subsystem present on various TI SoCs.
The PRUSS INTC enables various interrupts to be routed to multiple
different processors within the SoC.
2020-06-01 12:15:40 +03:00
config RISCV_INTC
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bool
2020-06-01 12:15:40 +03:00
depends on RISCV
2023-03-28 06:52:19 +03:00
select IRQ_DOMAIN_HIERARCHY
2020-06-01 12:15:40 +03:00
2018-07-26 17:27:00 +03:00
config SIFIVE_PLIC
2022-11-18 13:42:59 +03:00
bool
2018-07-26 17:27:00 +03:00
depends on RISCV
2019-12-10 14:11:11 +03:00
select IRQ_DOMAIN_HIERARCHY
2022-07-01 23:24:39 +03:00
select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
2019-10-02 17:44:52 +03:00
2019-12-25 00:11:07 +03:00
config EXYNOS_IRQ_COMBINER
bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
help
Say yes here to add support for the IRQ combiner devices embedded
in Samsung Exynos chips.
2022-07-20 13:51:31 +03:00
config IRQ_LOONGARCH_CPU
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
2022-10-20 17:25:35 +03:00
select LOONGSON_HTVEC
2022-08-08 11:53:19 +03:00
select LOONGSON_LIOINTC
select LOONGSON_EIOINTC
select LOONGSON_PCH_PIC
select LOONGSON_PCH_MSI
select LOONGSON_PCH_LPC
2022-07-20 13:51:31 +03:00
help
Support for the LoongArch CPU Interrupt Controller. For details of
irq chip hierarchy on LoongArch platforms please read the document
Documentation/loongarch/irq-chip-model.rst.
2020-03-25 06:54:54 +03:00
config LOONGSON_LIOINTC
bool "Loongson Local I/O Interrupt Controller"
depends on MACH_LOONGSON64
default y
select IRQ_DOMAIN
select GENERIC_IRQ_CHIP
help
Support for the Loongson Local I/O Interrupt Controller.
2022-07-20 13:51:30 +03:00
config LOONGSON_EIOINTC
bool "Loongson Extend I/O Interrupt Controller"
depends on LOONGARCH
depends on MACH_LOONGSON64
default MACH_LOONGSON64
select IRQ_DOMAIN_HIERARCHY
select GENERIC_IRQ_CHIP
help
Support for the Loongson3 Extend I/O Interrupt Vector Controller.
2020-03-25 06:54:57 +03:00
config LOONGSON_HTPIC
bool "Loongson3 HyperTransport PIC Controller"
2022-05-31 13:04:10 +03:00
depends on MACH_LOONGSON64 && MIPS
2020-03-25 06:54:57 +03:00
default y
select IRQ_DOMAIN
select GENERIC_IRQ_CHIP
help
Support for the Loongson-3 HyperTransport PIC Controller.
2020-05-28 18:27:49 +03:00
config LOONGSON_HTVEC
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bool "Loongson HyperTransport Interrupt Vector Controller"
2020-06-01 10:45:27 +03:00
depends on MACH_LOONGSON64
2020-05-28 18:27:49 +03:00
default MACH_LOONGSON64
select IRQ_DOMAIN_HIERARCHY
help
2022-05-31 13:04:10 +03:00
Support for the Loongson HyperTransport Interrupt Vector Controller.
2020-05-28 18:27:49 +03:00
2020-05-28 18:27:51 +03:00
config LOONGSON_PCH_PIC
bool "Loongson PCH PIC Controller"
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depends on MACH_LOONGSON64
2020-05-28 18:27:51 +03:00
default MACH_LOONGSON64
select IRQ_DOMAIN_HIERARCHY
select IRQ_FASTEOI_HIERARCHY_HANDLERS
help
Support for the Loongson PCH PIC Controller.
2020-05-28 18:27:53 +03:00
config LOONGSON_PCH_MSI
2020-05-30 15:11:12 +03:00
bool "Loongson PCH MSI Controller"
2022-07-20 13:51:28 +03:00
depends on MACH_LOONGSON64
2020-05-28 18:27:53 +03:00
depends on PCI
default MACH_LOONGSON64
select IRQ_DOMAIN_HIERARCHY
select PCI_MSI
help
Support for the Loongson PCH MSI Controller.
2022-07-20 13:51:26 +03:00
config LOONGSON_PCH_LPC
bool "Loongson PCH LPC Controller"
2022-09-16 10:19:26 +03:00
depends on LOONGARCH
2022-07-20 13:51:26 +03:00
depends on MACH_LOONGSON64
2022-09-16 10:19:26 +03:00
default MACH_LOONGSON64
2022-07-20 13:51:26 +03:00
select IRQ_DOMAIN_HIERARCHY
help
Support for the Loongson PCH LPC Controller.
2020-09-02 09:33:43 +03:00
config MST_IRQ
bool "MStar Interrupt Controller"
2020-10-14 16:17:03 +03:00
depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
2020-09-02 09:33:43 +03:00
default ARCH_MEDIATEK
select IRQ_DOMAIN
select IRQ_DOMAIN_HIERARCHY
help
Support MStar Interrupt Controller.
2021-04-06 15:09:17 +03:00
config WPCM450_AIC
bool "Nuvoton WPCM450 Advanced Interrupt Controller"
2021-04-08 10:56:27 +03:00
depends on ARCH_WPCM450
2021-04-06 15:09:17 +03:00
help
Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
2021-04-22 17:53:28 +03:00
config IRQ_IDT3243X
bool
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
2021-01-21 02:55:15 +03:00
config APPLE_AIC
bool "Apple Interrupt Controller (AIC)"
depends on ARM64
2021-04-13 15:21:58 +03:00
depends on ARCH_APPLE || COMPILE_TEST
2023-01-03 17:12:21 +03:00
select GENERIC_IRQ_IPI_MUX
2021-01-21 02:55:15 +03:00
help
Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
such as the M1.
2021-09-27 09:36:57 +03:00
config MCHP_EIC
bool "Microchip External Interrupt Controller"
depends on ARCH_AT91 || COMPILE_TEST
select IRQ_DOMAIN
select IRQ_DOMAIN_HIERARCHY
help
Support for Microchip External Interrupt Controller.
2022-06-28 09:26:48 +03:00
config SUNPLUS_SP7021_INTC
bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
default SOC_SP7021
help
Support for the Sunplus SP7021 Interrupt Controller IP core.
SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
chained controller, routing all interrupt source in P-Chip to
the primary controller on C-Chip.
2019-10-02 17:44:52 +03:00
endmenu
