Staging: bcm: Macros: Fixed multiple coding style violations.
Fixed multiple indentation issues. Signed-off-by: Benjamin James Wright <bwright.au@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Ben Wright
Greg Kroah-Hartman
parent
e5969d5574
commit
0118885849
@ -1,17 +1,17 @@
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/*************************************
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* Macros.h
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* Macros.h
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**************************************/
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#ifndef __MACROS_H__
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#ifndef __MACROS_H__
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#define __MACROS_H__
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#define TX_TIMER_PERIOD 10 //10 msec
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#define TX_TIMER_PERIOD 10 /*10 msec*/
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#define MAX_CLASSIFIERS 100
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//#define MAX_CLASSIFIERS_PER_SF 20
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/* #define MAX_CLASSIFIERS_PER_SF 20 */
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#define MAX_TARGET_DSX_BUFFERS 24
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#define MAX_CNTRL_PKTS 100
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#define MAX_DATA_PKTS 200
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#define MAX_ETH_SIZE 1536
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#define MAX_CNTRL_PKTS 100
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#define MAX_DATA_PKTS 200
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#define MAX_ETH_SIZE 1536
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#define MAX_CNTL_PKT_SIZE 2048
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#define MTU_SIZE 1400
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@ -20,102 +20,102 @@
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#define MAC_ADDR_REGISTER 0xbf60d000
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///////////Quality of Service///////////////////////////
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#define NO_OF_QUEUES 17
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#define HiPriority NO_OF_QUEUES-1
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#define LowPriority 0
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#define BE 2
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#define rtPS 4
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#define ERTPS 5
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#define UGS 6
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/* Quality of Service */
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#define NO_OF_QUEUES 17
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#define HiPriority (NO_OF_QUEUES-1)
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#define LowPriority 0
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#define BE 2
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#define rtPS 4
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#define ERTPS 5
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#define UGS 6
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#define BE_BUCKET_SIZE 1024*1024*100 //32kb
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#define rtPS_BUCKET_SIZE 1024*1024*100 //8kb
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#define MAX_ALLOWED_RATE 1024*1024*100
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#define TX_PACKET_THRESHOLD 10
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#define XSECONDS 1*HZ
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#define DSC_ACTIVATE_REQUEST 248
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#define QUEUE_DEPTH_OFFSET 0x1fc01000
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#define MAX_DEVICE_DESC_SIZE 2040
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#define MAX_CTRL_QUEUE_LEN 100
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#define MAX_APP_QUEUE_LEN 200
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#define MAX_LATENCY_ALLOWED 0xFFFFFFFF
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#define DEFAULT_UG_INTERVAL 250
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#define DEFAULT_UGI_FACTOR 4
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#define BE_BUCKET_SIZE (1024*1024*100) /* 32kb */
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#define rtPS_BUCKET_SIZE (1024*1024*100) /* 8kb */
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#define MAX_ALLOWED_RATE (1024*1024*100)
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#define TX_PACKET_THRESHOLD 10
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#define XSECONDS (1*HZ)
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#define DSC_ACTIVATE_REQUEST 248
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#define QUEUE_DEPTH_OFFSET 0x1fc01000
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#define MAX_DEVICE_DESC_SIZE 2040
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#define MAX_CTRL_QUEUE_LEN 100
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#define MAX_APP_QUEUE_LEN 200
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#define MAX_LATENCY_ALLOWED 0xFFFFFFFF
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#define DEFAULT_UG_INTERVAL 250
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#define DEFAULT_UGI_FACTOR 4
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#define DEFAULT_PERSFCOUNT 60
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#define MAX_CONNECTIONS 10
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#define MAX_CLASS_NAME_LENGTH 32
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#define DEFAULT_PERSFCOUNT 60
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#define MAX_CONNECTIONS 10
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#define MAX_CLASS_NAME_LENGTH 32
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#define ETH_LENGTH_OF_ADDRESS 6
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#define MAX_MULTICAST_ADDRESSES 32
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#define IP_LENGTH_OF_ADDRESS 4
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#define ETH_LENGTH_OF_ADDRESS 6
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#define MAX_MULTICAST_ADDRESSES 32
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#define IP_LENGTH_OF_ADDRESS 4
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#define IP_PACKET_ONLY_MODE 0
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#define ETH_PACKET_TUNNELING_MODE 1
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#define IP_PACKET_ONLY_MODE 0
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#define ETH_PACKET_TUNNELING_MODE 1
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////////////Link Request//////////////
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#define SET_MAC_ADDRESS_REQUEST 0
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#define SYNC_UP_REQUEST 1
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#define SYNCED_UP 2
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#define LINK_UP_REQUEST 3
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#define LINK_CONNECTED 4
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#define SYNC_UP_NOTIFICATION 2
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#define LINK_UP_NOTIFICATION 4
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/* Link Request */
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#define SET_MAC_ADDRESS_REQUEST 0
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#define SYNC_UP_REQUEST 1
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#define SYNCED_UP 2
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#define LINK_UP_REQUEST 3
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#define LINK_CONNECTED 4
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#define SYNC_UP_NOTIFICATION 2
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#define LINK_UP_NOTIFICATION 4
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#define LINK_NET_ENTRY 0x0002
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#define HMC_STATUS 0x0004
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#define HMC_STATUS 0x0004
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#define LINK_UP_CONTROL_REQ 0x83
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#define STATS_POINTER_REQ_STATUS 0x86
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#define NETWORK_ENTRY_REQ_PAYLOAD 198
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#define LINK_DOWN_REQ_PAYLOAD 226
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#define LINK_DOWN_REQ_PAYLOAD 226
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#define SYNC_UP_REQ_PAYLOAD 228
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#define STATISTICS_POINTER_REQ 237
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#define STATISTICS_POINTER_REQ 237
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#define LINK_UP_REQ_PAYLOAD 245
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#define LINK_UP_ACK 246
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#define STATS_MSG_SIZE 4
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#define INDEX_TO_DATA 4
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#define GO_TO_IDLE_MODE_PAYLOAD 210
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#define COME_UP_FROM_IDLE_MODE_PAYLOAD 211
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#define IDLE_MODE_SF_UPDATE_MSG 187
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#define GO_TO_IDLE_MODE_PAYLOAD 210
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#define COME_UP_FROM_IDLE_MODE_PAYLOAD 211
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#define IDLE_MODE_SF_UPDATE_MSG 187
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#define SKB_RESERVE_ETHERNET_HEADER 16
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#define SKB_RESERVE_PHS_BYTES 32
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#define SKB_RESERVE_ETHERNET_HEADER 16
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#define SKB_RESERVE_PHS_BYTES 32
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#define IP_PACKET_ONLY_MODE 0
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#define ETH_PACKET_TUNNELING_MODE 1
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#define IP_PACKET_ONLY_MODE 0
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#define ETH_PACKET_TUNNELING_MODE 1
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#define ETH_CS_802_3 1
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#define ETH_CS_802_1Q_VLAN 3
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#define IPV4_CS 1
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#define IPV6_CS 2
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#define ETH_CS_MASK 0x3f
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#define ETH_CS_802_3 1
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#define ETH_CS_802_1Q_VLAN 3
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#define IPV4_CS 1
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#define IPV6_CS 2
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#define ETH_CS_MASK 0x3f
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/** \brief Validity bit maps for TLVs in packet classification rule */
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#define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0
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#define PKT_CLASSIFICATION_VLANID_VALID 1
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#define PKT_CLASSIFICATION_USER_PRIORITY_VALID 0
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#define PKT_CLASSIFICATION_VLANID_VALID 1
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#ifndef MIN
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#define MIN(_a, _b) ((_a) < (_b)? (_a): (_b))
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#define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
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#endif
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/*Leader related terms */
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#define LEADER_STATUS 0x00
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#define LEADER_STATUS_TCP_ACK 0x1
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#define LEADER_SIZE sizeof(LEADER)
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#define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND)
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#define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND)
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#define CM_REQUEST_SIZE LEADER_SIZE + sizeof(stLocalSFChangeRequest)
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#define IDLE_REQ_SIZE sizeof(PACKETTOSEND)
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#define LEADER_STATUS 0x00
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#define LEADER_STATUS_TCP_ACK 0x1
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#define LEADER_SIZE sizeof(LEADER)
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#define MAC_ADDR_REQ_SIZE sizeof(PACKETTOSEND)
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#define SS_INFO_REQ_SIZE sizeof(PACKETTOSEND)
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#define CM_REQUEST_SIZE (LEADER_SIZE + sizeof(stLocalSFChangeRequest))
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#define IDLE_REQ_SIZE sizeof(PACKETTOSEND)
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#define MAX_TRANSFER_CTRL_BYTE_USB 2 * 1024
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#define MAX_TRANSFER_CTRL_BYTE_USB (2*1024)
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#define GET_MAILBOX1_REG_REQUEST 0x87
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#define GET_MAILBOX1_REG_RESPONSE 0x67
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@ -124,40 +124,40 @@
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#define TRANSMIT_NETWORK_DATA 0x00
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#define RECEIVED_NETWORK_DATA 0x20
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#define CM_RESPONSES 0xA0
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#define STATUS_RSP 0xA1
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#define LINK_CONTROL_RESP 0xA2
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#define IDLE_MODE_STATUS 0xA3
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#define STATS_POINTER_RESP 0xA6
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#define MGMT_MSG_INFO_SW_STATUS 0xA7
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#define AUTH_SS_HOST_MSG 0xA8
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#define CM_RESPONSES 0xA0
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#define STATUS_RSP 0xA1
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#define LINK_CONTROL_RESP 0xA2
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#define IDLE_MODE_STATUS 0xA3
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#define STATS_POINTER_RESP 0xA6
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#define MGMT_MSG_INFO_SW_STATUS 0xA7
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#define AUTH_SS_HOST_MSG 0xA8
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#define CM_DSA_ACK_PAYLOAD 247
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#define CM_DSC_ACK_PAYLOAD 248
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#define CM_DSD_ACK_PAYLOAD 249
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#define CM_DSDEACTVATE 250
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#define TOTAL_MASKED_ADDRESS_IN_BYTES 32
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#define CM_DSA_ACK_PAYLOAD 247
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#define CM_DSC_ACK_PAYLOAD 248
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#define CM_DSD_ACK_PAYLOAD 249
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#define CM_DSDEACTVATE 250
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#define TOTAL_MASKED_ADDRESS_IN_BYTES 32
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#define MAC_REQ 0
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#define LINK_RESP 1
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#define RSSI_INDICATION 2
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#define MAC_REQ 0
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#define LINK_RESP 1
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#define RSSI_INDICATION 2
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#define SS_INFO 4
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#define STATISTICS_INFO 5
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#define CM_INDICATION 6
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#define PARAM_RESP 7
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#define BUFFER_1K 1024
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#define BUFFER_2K BUFFER_1K*2
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#define BUFFER_4K BUFFER_2K*2
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#define BUFFER_8K BUFFER_4K*2
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#define BUFFER_16K BUFFER_8K*2
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#define DOWNLINK_DIR 0
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#define UPLINK_DIR 1
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#define SS_INFO 4
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#define STATISTICS_INFO 5
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#define CM_INDICATION 6
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#define PARAM_RESP 7
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#define BUFFER_1K 1024
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#define BUFFER_2K (BUFFER_1K*2)
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#define BUFFER_4K (BUFFER_2K*2)
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#define BUFFER_8K (BUFFER_4K*2)
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#define BUFFER_16K (BUFFER_8K*2)
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#define DOWNLINK_DIR 0
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#define UPLINK_DIR 1
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#define BCM_SIGNATURE "BECEEM"
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#define BCM_SIGNATURE "BECEEM"
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#define GPIO_OUTPUT_REGISTER 0x0F00003C
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#define GPIO_OUTPUT_REGISTER 0x0F00003C
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#define BCM_GPIO_OUTPUT_SET_REG 0x0F000040
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#define BCM_GPIO_OUTPUT_CLR_REG 0x0F000044
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#define GPIO_MODE_REGISTER 0x0F000034
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@ -165,44 +165,43 @@
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typedef struct _LINK_STATE {
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UCHAR ucLinkStatus;
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UCHAR bIdleMode;
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UCHAR bShutdownMode;
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}LINK_STATE, *PLINK_STATE;
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UCHAR ucLinkStatus;
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UCHAR bIdleMode;
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UCHAR bShutdownMode;
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} LINK_STATE, *PLINK_STATE;
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enum enLinkStatus {
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WAIT_FOR_SYNC = 1,
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PHY_SYNC_ACHIVED = 2,
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LINKUP_IN_PROGRESS = 3,
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LINKUP_DONE = 4,
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DREG_RECEIVED = 5,
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LINK_STATUS_RESET_RECEIVED = 6,
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PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7,
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LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8,
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COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW =9
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WAIT_FOR_SYNC = 1,
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PHY_SYNC_ACHIVED = 2,
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LINKUP_IN_PROGRESS = 3,
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LINKUP_DONE = 4,
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DREG_RECEIVED = 5,
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LINK_STATUS_RESET_RECEIVED = 6,
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PERIODIC_WAKE_UP_NOTIFICATION_FRM_FW = 7,
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LINK_SHUTDOWN_REQ_FROM_FIRMWARE = 8,
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COMPLETE_WAKE_UP_NOTIFICATION_FRM_FW = 9
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};
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typedef enum _E_PHS_DSC_ACTION
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{
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eAddPHSRule=0,
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typedef enum _E_PHS_DSC_ACTION {
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eAddPHSRule = 0,
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eSetPHSRule,
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eDeletePHSRule,
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eDeleteAllPHSRules
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}E_PHS_DSC_ACTION;
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} E_PHS_DSC_ACTION;
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#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 // Host to Mac
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#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 // Mac to Host
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#define MASK_DISABLE_HEADER_SUPPRESSION 0x10 //0b000010000
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#define MINIMUM_PENDING_DESCRIPTORS 5
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#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_REQ 0x89 /* Host to Mac */
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#define CM_CONTROL_NEWDSX_MULTICLASSIFIER_RESP 0xA9 /* Mac to Host */
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#define MASK_DISABLE_HEADER_SUPPRESSION 0x10 /* 0b000010000 */
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#define MINIMUM_PENDING_DESCRIPTORS 5
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#define SHUTDOWN_HOSTINITIATED_REQUESTPAYLOAD 0xCC
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#define SHUTDOWN_ACK_FROM_DRIVER 0x1
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#define SHUTDOWN_NACK_FROM_DRIVER 0x2
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#define LINK_SYNC_UP_SUBTYPE 0x0001
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#define LINK_SYNC_DOWN_SUBTYPE 0x0001
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#define LINK_SYNC_UP_SUBTYPE 0x0001
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#define LINK_SYNC_DOWN_SUBTYPE 0x0001
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@ -226,9 +225,9 @@ typedef enum _E_PHS_DSC_ACTION
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#define MAX_PENDING_CTRL_PACKET (MAX_CTRL_QUEUE_LEN-10)
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#define WIMAX_MAX_MTU (MTU_SIZE + ETH_HLEN)
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#define WIMAX_MAX_MTU (MTU_SIZE + ETH_HLEN)
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#define AUTO_LINKUP_ENABLE 0x2
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#define AUTO_SYNC_DISABLE 0x1
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#define AUTO_SYNC_DISABLE 0x1
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#define AUTO_FIRM_DOWNLOAD 0x1
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#define SETTLE_DOWN_TIME 50
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@ -242,9 +241,9 @@ typedef enum _E_PHS_DSC_ACTION
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#define TARGET_CAN_NOT_GO_TO_IDLE_MODE 3
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#define IDLE_MODE_PAYLOAD_LENGTH 8
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#define IP_HEADER(Buffer) ((IPHeaderFormat*)(Buffer))
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#define IPV4 4
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#define IP_VERSION(byte) (((byte&0xF0)>>4))
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#define IP_HEADER(Buffer) ((IPHeaderFormat *)(Buffer))
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#define IPV4 4
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#define IP_VERSION(byte) (((byte&0xF0)>>4))
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#define SET_MAC_ADDRESS 193
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#define SET_MAC_ADDRESS_RESPONSE 236
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@ -263,15 +262,15 @@ typedef enum _E_PHS_DSC_ACTION
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#define INVALID_QUEUE_INDEX NO_OF_QUEUES
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#define INVALID_PID (pid_t)-1
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#define DDR_80_MHZ 0
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#define DDR_100_MHZ 1
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#define DDR_120_MHZ 2 // Additional Frequency for T3LP
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#define DDR_133_MHZ 3
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#define DDR_140_MHZ 4 // Not Used (Reserved for future)
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#define DDR_160_MHZ 5 // Additional Frequency for T3LP
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#define DDR_180_MHZ 6 // Not Used (Reserved for future)
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#define DDR_200_MHZ 7 // Not Used (Reserved for future)
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#define INVALID_PID ((pid_t)-1)
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#define DDR_80_MHZ 0
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#define DDR_100_MHZ 1
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#define DDR_120_MHZ 2 /* Additional Frequency for T3LP */
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#define DDR_133_MHZ 3
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#define DDR_140_MHZ 4 /* Not Used (Reserved for future) */
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#define DDR_160_MHZ 5 /* Additional Frequency for T3LP */
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#define DDR_180_MHZ 6 /* Not Used (Reserved for future) */
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#define DDR_200_MHZ 7 /* Not Used (Reserved for future) */
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#define MIPS_200_MHZ 0
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#define MIPS_160_MHZ 1
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@ -291,27 +290,27 @@ typedef enum _E_PHS_DSC_ACTION
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#define EEPROM_REJECT_REG_3 0x0f003008
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#define EEPROM_REJECT_REG_4 0x0f003020
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#define EEPROM_REJECT_MASK 0x0fffffff
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#define VSG_MODE 0x3
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#define VSG_MODE 0x3
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/* Idle Mode Related Registers */
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#define DEBUG_INTERRUPT_GENERATOR_REGISTOR 0x0F00007C
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#define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC
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#define SW_ABORT_IDLEMODE_LOC 0x0FF01FFC
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#define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e
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#define DEVICE_INT_OUT_EP_REG0 0x0F011870
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#define DEVICE_INT_OUT_EP_REG1 0x0F011874
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#define SW_ABORT_IDLEMODE_PATTERN 0xd0ea1d1e
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#define DEVICE_INT_OUT_EP_REG0 0x0F011870
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#define DEVICE_INT_OUT_EP_REG1 0x0F011874
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#define BIN_FILE "/lib/firmware/macxvi200.bin"
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#define CFG_FILE "/lib/firmware/macxvi.cfg"
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#define SF_MAX_ALLOWED_PACKETS_TO_BACKUP 128
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#define MIN_VAL(x,y) ((x)<(y)?(x):(y))
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#define MIN_VAL(x, y) ((x) < (y) ? (x) : (y))
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#define MAC_ADDRESS_SIZE 6
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#define EEPROM_COMMAND_Q_REG 0x0F003018
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#define EEPROM_READ_DATA_Q_REG 0x0F003020
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#define CHIP_ID_REG 0x0F000000
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#define GPIO_MODE_REG 0x0F000034
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#define GPIO_OUTPUT_REG 0x0F00003C
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#define WIMAX_MAX_ALLOWED_RATE 1024*1024*50
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#define CHIP_ID_REG 0x0F000000
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#define GPIO_MODE_REG 0x0F000034
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#define GPIO_OUTPUT_REG 0x0F00003C
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#define WIMAX_MAX_ALLOWED_RATE (1024*1024*50)
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#define T3 0xbece0300
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#define TARGET_SFID_TXDESC_MAP_LOC 0xBFFFF400
|
||||
@ -319,31 +318,29 @@ typedef enum _E_PHS_DSC_ACTION
|
||||
#define RWM_READ 0
|
||||
#define RWM_WRITE 1
|
||||
|
||||
#define T3LPB 0xbece3300
|
||||
#define BCS220_2 0xbece3311
|
||||
#define BCS220_2BC 0xBECE3310
|
||||
#define BCS250_BC 0xbece3301
|
||||
#define BCS220_3 0xbece3321
|
||||
#define T3LPB 0xbece3300
|
||||
#define BCS220_2 0xbece3311
|
||||
#define BCS220_2BC 0xBECE3310
|
||||
#define BCS250_BC 0xbece3301
|
||||
#define BCS220_3 0xbece3321
|
||||
|
||||
|
||||
#define HPM_CONFIG_LDO145 0x0F000D54
|
||||
#define HPM_CONFIG_MSW 0x0F000D58
|
||||
#define HPM_CONFIG_LDO145 0x0F000D54
|
||||
#define HPM_CONFIG_MSW 0x0F000D58
|
||||
|
||||
#define T3B 0xbece0310
|
||||
typedef enum eNVM_TYPE
|
||||
{
|
||||
typedef enum eNVM_TYPE {
|
||||
NVM_AUTODETECT = 0,
|
||||
NVM_EEPROM,
|
||||
NVM_FLASH,
|
||||
NVM_UNKNOWN
|
||||
}NVM_TYPE;
|
||||
} NVM_TYPE;
|
||||
|
||||
typedef enum ePMU_MODES
|
||||
{
|
||||
typedef enum ePMU_MODES {
|
||||
HYBRID_MODE_7C = 0,
|
||||
INTERNAL_MODE_6 = 1,
|
||||
HYBRID_MODE_6 = 2
|
||||
}PMU_MODE;
|
||||
} PMU_MODE;
|
||||
|
||||
#define MAX_RDM_WRM_RETIRES 1
|
||||
|
||||
@ -360,4 +357,4 @@ enum eAbortPattern {
|
||||
#define SKB_CB_LATENCY_OFFSET 1
|
||||
#define SKB_CB_TCPACK_OFFSET 2
|
||||
|
||||
#endif //__MACROS_H__
|
||||
#endif /* __MACROS_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user